O_JSR): Do not allow VECIND addressing for non-SX processors.

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 684a2e7c4622b2574715584117551703a9e5120b..b8ca48603631879659bd7574d37ed45feefe0a1a 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,9 @@
+2004-08-13  Nick Clifton  <nickc@redhat.com>
+
+       PR/301
+       * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
+       processors.
+
 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 
        * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.

diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h
index 29374df5b4fe3431348ceca0567c6543ae66667f..fe1097fd2863fb63824f8f24e7dba8f26e329911 100644 (file)
--- a/include/opcode/h8300.h
+++ b/include/opcode/h8300.h
@@ -1418,7 +1418,7 @@ struct h8_opcode h8_opcodes[] =
   {O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}},
 
   {O (O_JSR, SN), AV_H8,   8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}},
-  {O (O_JSR, SN), AV_H8,   8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}},
+  {O (O_JSR, SN), AV_H8SX, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}},
 
   {O (O_LDC, SB), AV_H8,   2, "ldc", {{IMM8,       CCR     | DST, E}}, {{                           0x0, 0x7, IMM8LIST, E}}},
   {O (O_LDC, SB), AV_H8S,  2, "ldc", {{IMM8,       EXR     | DST, E}}, {{0x0, 0x1, 0x4,  EXR | DST, 0x0, 0x7, IMM8LIST, E}}},