Add "check -mapped"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/CHANGELOG b/CHANGELOG
index c1ffaa44a18030ad9630a65c2904531d6644d50f..1fc139d498d58d2a7431b2040ae86f8a0583cf05 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -50,6 +50,7 @@ Yosys 0.9 .. Yosys 0.9-dev
     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
     - "synth_ice40 -dsp" to infer DSP blocks
     - Added latch support to synth_xilinx
+    - Added "check -mapped"
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------

diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc
index 64697c134bf666b0934e1d5ded0bfcedd987f0c5..87dc34209511e403bc3f76b0527ccd0a33ed7e12 100644 (file)
--- a/passes/cmds/check.cc
+++ b/passes/cmds/check.cc
@@ -47,6 +47,9 @@ struct CheckPass : public Pass {
                log("When called with -initdrv then this command also checks for wires which have\n");
                log("the 'init' attribute set and aren't driven by a FF cell type.\n");
                log("\n");
+               log("When called with -mapped then this command also checks for internal cells\n");
+               log("that have not been mapped to cells of the target architecture.\n");
+               log("\n");
                log("When called with -assert then the command will produce an error if any\n");
                log("problems are found in the current design.\n");
                log("\n");
@@ -56,6 +59,7 @@ struct CheckPass : public Pass {
                int counter = 0;
                bool noinit = false;
                bool initdrv = false;
+               bool mapped = false;
                bool assert_mode = false;
 
                size_t argidx;
@@ -68,6 +72,10 @@ struct CheckPass : public Pass {
                                initdrv = true;
                                continue;
                        }
+                       if (args[argidx] == "-mapped") {
+                               mapped = true;
+                               continue;
+                       }
                        if (args[argidx] == "-assert") {
                                assert_mode = true;
                                continue;
@@ -135,29 +143,35 @@ struct CheckPass : public Pass {
                        TopoSort<string> topo;
 
                        for (auto cell : module->cells())
-                       for (auto &conn : cell->connections()) {
-                               SigSpec sig = sigmap(conn.second);
-                               bool logic_cell = yosys_celltypes.cell_evaluable(cell->type);
-                               if (cell->input(conn.first))
-                                       for (auto bit : sig)
-                                               if (bit.wire) {
+                       {
+                               if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
+                                       log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", log_id(module), log_id(cell), log_id(cell->type));
+                                       counter++;
+                               }
+                               for (auto &conn : cell->connections()) {
+                                       SigSpec sig = sigmap(conn.second);
+                                       bool logic_cell = yosys_celltypes.cell_evaluable(cell->type);
+                                       if (cell->input(conn.first))
+                                               for (auto bit : sig)
+                                                       if (bit.wire) {
+                                                               if (logic_cell)
+                                                                       topo.edge(stringf("wire %s", log_signal(bit)),
+                                                                                       stringf("cell %s (%s)", log_id(cell), log_id(cell->type)));
+                                                               used_wires.insert(bit);
+                                                       }
+                                       if (cell->output(conn.first))
+                                               for (int i = 0; i < GetSize(sig); i++) {
                                                        if (logic_cell)
-                                                               topo.edge(stringf("wire %s", log_signal(bit)),
-                                                                               stringf("cell %s (%s)", log_id(cell), log_id(cell->type)));
-                                                       used_wires.insert(bit);
+                                                               topo.edge(stringf("cell %s (%s)", log_id(cell), log_id(cell->type)),
+                                                                               stringf("wire %s", log_signal(sig[i])));
+                                                       if (sig[i].wire)
+                                                               wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)",
+                                                                               log_id(conn.first), i, log_id(cell), log_id(cell->type)));
                                                }
-                               if (cell->output(conn.first))
-                                       for (int i = 0; i < GetSize(sig); i++) {
-                                               if (logic_cell)
-                                                       topo.edge(stringf("cell %s (%s)", log_id(cell), log_id(cell->type)),
-                                                                       stringf("wire %s", log_signal(sig[i])));
-                                               if (sig[i].wire)
-                                                       wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)",
-                                                                       log_id(conn.first), i, log_id(cell), log_id(cell->type)));
-                                       }
-                               if (!cell->input(conn.first) && cell->output(conn.first))
-                                       for (auto bit : sig)
-                                               if (bit.wire) wire_drivers_count[bit]++;
+                                       if (!cell->input(conn.first) && cell->output(conn.first))
+                                               for (auto bit : sig)
+                                                       if (bit.wire) wire_drivers_count[bit]++;
+                               }
                        }
 
                        pool<SigBit> init_bits;