soc_core: add cpu_endianness

diff --git a/litex/soc/integration/cpu_interface.py b/litex/soc/integration/cpu_interface.py
index ad4e8a33b9fa058879f035511ac88a539691bb92..bc934cf3e70e3c60ab2b725d63fd1130eaecbb62 100644 (file)
--- a/litex/soc/integration/cpu_interface.py
+++ b/litex/soc/integration/cpu_interface.py
@@ -6,6 +6,7 @@ from migen import *
 from litex.soc.interconnect.csr import CSRStatus
 
 cpu_endianness = {
+    None: "big",
     "lm32": "big",
     "or1k": "big",
     "picorv32": "little",

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 61e58687408967764a6f4236e64bb684714c6d6f..6a7bbd40f93920c80649a02633395708003521b2 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -7,6 +7,7 @@ from litex.soc.cores import identifier, timer, uart
 from litex.soc.cores.cpu import lm32, mor1kx, picorv32, vexriscv
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr
+from litex.soc.integration.cpu_interface import cpu_endianness
 
 
 __all__ = ["mem_decoder", "SoCCore", "soc_core_args", "soc_core_argdict"]
@@ -105,6 +106,7 @@ class SoCCore(Module):
 
         self.cpu_type = cpu_type
         self.cpu_variant = cpu_variant
+        self.cpu_endianness = cpu_endianness[cpu_type]
         if integrated_rom_size:
             cpu_reset_address = self.mem_map["rom"]
         self.cpu_reset_address = cpu_reset_address