sdram/module: add speedgrate note for IS42S16160 and AS4C16M16

diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py
index 109e51d061f5ce31108618a1b75bf3479d845bf0..e41bced063c3ed1292f170a9056972ddea62beee 100644 (file)
--- a/misoclib/mem/sdram/module.py
+++ b/misoclib/mem/sdram/module.py
@@ -49,6 +49,7 @@ class IS42S16160(SDRAMModule):
                "nrows":        8192,
                "ncols":        512
        }
+       # Note: timings for -7 speedgrade (add support for others speedgrades)
        timing_settings = {
                "tRP":          20,
                "tRCD":         20,
@@ -85,6 +86,7 @@ class AS4C16M16(SDRAMModule):
                "nrows":        8192,
                "ncols":        512
        }
+       # Note: timings for -6 speedgrade (add support for others speedgrades)
        timing_settings = {
                "tRP":          18,
                "tRCD":         18,