* avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros.

	Move related opcodes closer to each other.
	Minor changes in comments, list undefined opcodes.

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index a4ea015968d2266ccc077cf43e15235e95337ca9..c5c067452844fb6880d606f466e4e8512f3405f1 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,9 @@
+2000-07-29  Marek Michalkiewicz  <marekm@linux.org.pl>
+
+       * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros.
+       Move related opcodes closer to each other.
+       Minor changes in comments, list undefined opcodes.
+
 2000-07-26  Dave Brolley  <brolley@redhat.com>
 
        * cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned.

diff --git a/include/opcode/avr.h b/include/opcode/avr.h
index 1f0251450f89049117e6e6f41675d385bb02a9fa..393ca22d66b19c0101575725377178ae9077f1ba 100644 (file)
--- a/include/opcode/avr.h
+++ b/include/opcode/avr.h
@@ -45,6 +45,22 @@
                       || (x) == 'a'            \
                       || (x) == 'v')
 
+/* Undefined combination of operands - does the register
+   operand overlap with pre-decremented or post-incremented
+   pointer register (like ld r31,Z+)?  */
+#define AVR_UNDEF_P(x) (((x) & 0xFFED) == 0x91E5 ||            \
+  ((x) & 0xFDEF) == 0x91AD || ((x) & 0xFDEF) == 0x91AE ||      \
+  ((x) & 0xFDEF) == 0x91C9 || ((x) & 0xFDEF) == 0x91CA ||      \
+  ((x) & 0xFDEF) == 0x91E1 || ((x) & 0xFDEF) == 0x91E2)
+
+/* Is this a skip instruction {cpse,sbic,sbis,sbrc,sbrs}?  */
+#define AVR_SKIP_P(x) (((x) & 0xFC00) == 0x1000 ||             \
+  ((x) & 0xFD00) == 0x9900 || ((x) & 0xFC08) == 0xFC00)
+
+/* Is this `ldd r,b+0' or `std b+0,r' (b={Y,Z}, disassembled as
+   `ld r,b' or `st b,r' respectively - next opcode entry)?  */
+#define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000)
+
 /* constraint letters
    r - any register
    d - `ldi' register (r16-r31)
@@ -57,16 +73,37 @@
    M - immediate value from 0 to 255
    n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible
    s - immediate value from 0 to 7
-   P - Port address value from 0 to 64. (in, out)
-   p - Port address value from 0 to 32. (cbi, sbi, sbic, sbis)
-   K - immediate value from 0 to 64 (used in `adiw', `sbiw')
+   P - Port address value from 0 to 63. (in, out)
+   p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
+   K - immediate value from 0 to 63 (used in `adiw', `sbiw')
    i - immediate value
    l - signed pc relative offset from -64 to 63
    L - signed pc relative offset from -2048 to 2047
-   h - absolut code address (call, jmp)
+   h - absolute code address (call, jmp)
    S - immediate value from 0 to 7 (S = s << 4)
    ? - use this opcode entry if no parameters, else use next opcode entry
-*/
+
+   Order is important - some binary opcodes have more than one name,
+   the disassembler will only see the first match.
+
+   Remaining undefined opcodes (1700 total - some of them might work
+   as normal instructions if not all of the bits are decoded):
+
+    0x0001...0x00ff    (255) (known to be decoded as `nop' by the old core)
+   "100100xxxxxxx011"  (128) 0x9[0-3][0-9a-f][3b]
+   "100100xxxxxx1000"   (64) 0x9[0-3][0-9a-f]8
+   "1001001xxxxx01xx"  (128) 0x9[23][0-9a-f][4-7]
+   "1001010xxxxx0100"   (32) 0x9[45][0-9a-f]4
+   "1001010x001x1001"    (4) 0x9[45][23]9
+   "1001010x01xx1001"    (8) 0x9[45][4-7]9
+   "1001010x1xxx1001"   (16) 0x9[45][8-9a-f]9
+   "1001010xxxxx1011"   (32) 0x9[45][0-9a-f]b
+   "10010101001x1000"    (2) 0x95[23]8
+   "1001010101xx1000"    (4) 0x95[4-7]8
+   "1001010110x11000"    (2) 0x95[9b]8
+   "1001010111111000"    (1) 0x95f8 (`espm' removed in databook update)
+   "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f]
+ */
 
 AVR_INSN (clc,  "",    "1001010010001000", 1, AVR_ISA_1200, 0x9488)
 AVR_INSN (clh,  "",    "1001010011011000", 1, AVR_ISA_1200, 0x94d8)
@@ -76,23 +113,31 @@ AVR_INSN (cls,  "",    "1001010011001000", 1, AVR_ISA_1200, 0x94c8)
 AVR_INSN (clt,  "",    "1001010011101000", 1, AVR_ISA_1200, 0x94e8)
 AVR_INSN (clv,  "",    "1001010010111000", 1, AVR_ISA_1200, 0x94b8)
 AVR_INSN (clz,  "",    "1001010010011000", 1, AVR_ISA_1200, 0x9498)
+
+AVR_INSN (sec,  "",    "1001010000001000", 1, AVR_ISA_1200, 0x9408)
+AVR_INSN (seh,  "",    "1001010001011000", 1, AVR_ISA_1200, 0x9458)
+AVR_INSN (sei,  "",    "1001010001111000", 1, AVR_ISA_1200, 0x9478)
+AVR_INSN (sen,  "",    "1001010000101000", 1, AVR_ISA_1200, 0x9428)
+AVR_INSN (ses,  "",    "1001010001001000", 1, AVR_ISA_1200, 0x9448)
+AVR_INSN (set,  "",    "1001010001101000", 1, AVR_ISA_1200, 0x9468)
+AVR_INSN (sev,  "",    "1001010000111000", 1, AVR_ISA_1200, 0x9438)
+AVR_INSN (sez,  "",    "1001010000011000", 1, AVR_ISA_1200, 0x9418)
+
+   /* Same as {cl,se}[chinstvz] above.  */
+AVR_INSN (bclr, "S",   "100101001SSS1000", 1, AVR_ISA_1200, 0x9488)
+AVR_INSN (bset, "S",   "100101000SSS1000", 1, AVR_ISA_1200, 0x9408)
+
 AVR_INSN (icall,"",    "1001010100001001", 1, AVR_ISA_2xxx, 0x9509)
 AVR_INSN (ijmp, "",    "1001010000001001", 1, AVR_ISA_2xxx, 0x9409)
+
 AVR_INSN (lpm,  "?",   "1001010111001000", 1, AVR_ISA_TINY1,0x95c8)
 AVR_INSN (lpm,  "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004)
 AVR_INSN (elpm, "?",   "1001010111011000", 1, AVR_ISA_ELPM, 0x95d8)
 AVR_INSN (elpm, "r,z", "1001000ddddd011+", 1, AVR_ISA_ELPMX,0x9006)
+
 AVR_INSN (nop,  "",    "0000000000000000", 1, AVR_ISA_1200, 0x0000)
 AVR_INSN (ret,  "",    "1001010100001000", 1, AVR_ISA_1200, 0x9508)
 AVR_INSN (reti, "",    "1001010100011000", 1, AVR_ISA_1200, 0x9518)
-AVR_INSN (sec,  "",    "1001010000001000", 1, AVR_ISA_1200, 0x9408)
-AVR_INSN (seh,  "",    "1001010001011000", 1, AVR_ISA_1200, 0x9458)
-AVR_INSN (sei,  "",    "1001010001111000", 1, AVR_ISA_1200, 0x9478)
-AVR_INSN (sen,  "",    "1001010000101000", 1, AVR_ISA_1200, 0x9428)
-AVR_INSN (ses,  "",    "1001010001001000", 1, AVR_ISA_1200, 0x9448)
-AVR_INSN (set,  "",    "1001010001101000", 1, AVR_ISA_1200, 0x9468)
-AVR_INSN (sev,  "",    "1001010000111000", 1, AVR_ISA_1200, 0x9438)
-AVR_INSN (sez,  "",    "1001010000011000", 1, AVR_ISA_1200, 0x9418)
 AVR_INSN (sleep,"",    "1001010110001000", 1, AVR_ISA_1200, 0x9588)
 AVR_INSN (wdr,  "",    "1001010110101000", 1, AVR_ISA_1200, 0x95a8)
 AVR_INSN (spm,  "",    "1001010111101000", 1, AVR_ISA_SPM,  0x95e8)
@@ -110,6 +155,7 @@ AVR_INSN (or,   "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800)
 AVR_INSN (sbc,  "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800)
 AVR_INSN (sub,  "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800)
 
+   /* Shorthand for {eor,add,adc,and} r,r above.  */
 AVR_INSN (clr,  "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400)
 AVR_INSN (lsl,  "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
 AVR_INSN (rol,  "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
@@ -118,11 +164,15 @@ AVR_INSN (tst,  "r=r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000)
 AVR_INSN (andi, "d,M", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
   /*XXX special case*/
 AVR_INSN (cbr,  "d,n", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
-AVR_INSN (cpi,  "d,M", "0011KKKKddddKKKK", 1, AVR_ISA_1200, 0x3000)
+
 AVR_INSN (ldi,  "d,M", "1110KKKKddddKKKK", 1, AVR_ISA_1200, 0xe000)
+AVR_INSN (ser,  "d",   "11101111dddd1111", 1, AVR_ISA_1200, 0xef0f)
+
 AVR_INSN (ori,  "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000)
-AVR_INSN (sbci, "d,M", "0100KKKKddddKKKK", 1, AVR_ISA_1200, 0x4000)
 AVR_INSN (sbr,  "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000)
+
+AVR_INSN (cpi,  "d,M", "0011KKKKddddKKKK", 1, AVR_ISA_1200, 0x3000)
+AVR_INSN (sbci, "d,M", "0100KKKKddddKKKK", 1, AVR_ISA_1200, 0x4000)
 AVR_INSN (subi, "d,M", "0101KKKKddddKKKK", 1, AVR_ISA_1200, 0x5000)
 
 AVR_INSN (sbrc, "r,s", "1111110rrrrr0sss", 1, AVR_ISA_1200, 0xfc00)
@@ -160,6 +210,7 @@ AVR_INSN (brts, "l",   "111100lllllll110", 1, AVR_ISA_1200, 0xf006)
 AVR_INSN (brvc, "l",   "111101lllllll011", 1, AVR_ISA_1200, 0xf403)
 AVR_INSN (brvs, "l",   "111100lllllll011", 1, AVR_ISA_1200, 0xf003)
 
+   /* Same as br?? above.  */
 AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400)
 AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000)
 
@@ -178,12 +229,9 @@ AVR_INSN (neg,  "r",   "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401)
 AVR_INSN (pop,  "r",   "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f)
 AVR_INSN (push, "r",   "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f)
 AVR_INSN (ror,  "r",   "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407)
-AVR_INSN (ser,  "d",   "11101111dddd1111", 1, AVR_ISA_1200, 0xef0f)
 AVR_INSN (swap, "r",   "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402)
 
-AVR_INSN (bclr, "S",   "100101001SSS1000", 1, AVR_ISA_1200, 0x9488)
-AVR_INSN (bset, "S",   "100101000SSS1000", 1, AVR_ISA_1200, 0x9408)
-
+   /* Known to be decoded as `nop' by the old core.  */
 AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MUL,  0x0100)
 AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL,  0x0200)
 AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL,  0x0300)
@@ -193,15 +241,16 @@ AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL,  0x0388)
 
 AVR_INSN (sts,  "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200)
 AVR_INSN (lds,  "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000)
+
+   /* Special case for b+0, `e' must be next entry after `b',
+      b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X.  */
 AVR_INSN (ldd,  "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000)
-AVR_INSN (std,  "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200)
-  /* ee = {X=11,Y=10,Z=00, 0) */
 AVR_INSN (ld,   "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000)
+AVR_INSN (std,  "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200)
 AVR_INSN (st,   "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200)
 
-     /* these are for devices that don't exist yet */
-/* espm (0x95f8) removed in databook update, use spm with RAMPZ:Z */
-     /* >128K program memory (PC = EIND:Z) */
+   /* These are for devices that don't exist yet
+      (>128K program memory, PC = EIND:Z).  */
 AVR_INSN (eicall, "",  "1001010100011001", 1, AVR_ISA_EIND, 0x9519)
 AVR_INSN (eijmp, "",   "1001010000011001", 1, AVR_ISA_EIND, 0x9419)