Fixed handling of [a-fxz?] in decimal constants

diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index 5dc149dfd9f7cb43da5311ada4de07d36d36a3d5..d54f1428e508d811be1d33327976bedc866bce2b 100644 (file)
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -48,7 +48,9 @@ static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
 {
        int carry = 0;
        for (size_t i = 0; i < digits.size(); i++) {
-               log_assert(digits[i] < 10);
+               if (digits[i] >= 10)
+                       log_error("Invalid use of [a-fxz?] in decimal constant at %s:%d.\n",
+                               current_filename.c_str(), get_line_num());
                digits[i] += carry * 10;
                carry = digits[i] % 2;
                digits[i] /= 2;
@@ -91,6 +93,9 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
                str++;
        }
 
+       if (base == 10 && GetSize(digits) == 1 && digits.front() >= 0xf0)
+               base = 2;
+
        if (base == 10) {
                data.clear();
                if (len_in_bits < 0) {
@@ -138,7 +143,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
                AstNode *ret = const2ast(code, case_type);
                if (std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end())
                        log_warning("Yosys does not support tri-state logic at the moment. (%s:%d)\n",
-                               current_filename.c_str(), frontend_verilog_yyget_lineno());
+                               current_filename.c_str(), get_line_num());
                return ret;
        }
 

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index abdd1ff8a046a2d6350633affb37e136b8ca8309..bd7f5c9f29c25695557a94ac3f206b93a1b39414 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3280,6 +3280,10 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
 {
        cover("kernel.rtlil.sigspec.parse");
 
+       AST::current_filename = "input";
+       AST::use_internal_line_num();
+       AST::set_line_num(0);
+
        std::vector<std::string> tokens;
        sigspec_parse_split(tokens, str, ',');