Add ram file to synthesis build dependencies

Signed-off-by: Michael Neuling <mikey@neuling.org>

diff --git a/Makefile b/Makefile
index f20d048cd39aef2c917b90c097a8a0ad86a30ae2..769a6bd7e5cd37108df918fe600fcee58017c158 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -175,10 +175,10 @@ fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
 
 synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 
-microwatt.json: $(synth_files)
+microwatt.json: $(synth_files) $(RAM_INIT_FILE)
        $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@" $(uart_files)
 
-microwatt.v: $(synth_files)
+microwatt.v: $(synth_files) $(RAM_INIT_FILE)
        $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@" $(uart_files)
 
 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall