re PR target/65915 (FAIL: gcc.target/i386/avx512f-vrndscalepd-2.c (internal compiler...

PR target/65915
* config/i386/i386.md (vector convert to float spltiter): Check for
xmm16+, when splitting scalar float conversion.
* config/i386/sse.md (sse2_cvtsi2sd): Support EVEX version.

testsuite/ChangeLog:

PR target/65915
* gcc.target/i386/pr65915.c: New.

From-SVN: r222811

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d8d673c6c6d68617caa9ad8ce027fa2310e817e8..2fcfad939e1110d9600fea80a7c1984dde3754e5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2015-05-05  Ilya Tocar  <ilya.tocar@intel.com>
+
+       PR target/65915
+       * config/i386/i386.md (vector convert to float spltiter): Check for
+       xmm16+, when splitting scalar float conversion.
+       * config/i386/sse.md (sse2_cvtsi2sd): Support EVEX version.
+
 2015-05-05  Nick Clifton  <nickc@redhat.com>
 
        * config/msp430/msp430-opts.h (enum msp430_regions): New.

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 0e941b6be6683a290db7296e3281291c8434e637..fc320f67b54311b7b11b6cb46212c2a0770a36f0 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -4897,7 +4897,9 @@
   "TARGET_SSE2 && TARGET_SSE_MATH
    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
    && reload_completed && SSE_REG_P (operands[0])
-   && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)"
+   && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)
+   && (!EXT_REX_SSE_REG_P (operands[0])
+       || TARGET_AVX512VL)"
   [(const_int 0)]
 {
   operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
@@ -4921,7 +4923,9 @@
   "TARGET_SSE2 && TARGET_SSE_MATH
    && TARGET_SSE_PARTIAL_REG_DEPENDENCY
    && optimize_function_for_speed_p (cfun)
-   && reload_completed && SSE_REG_P (operands[0])"
+   && reload_completed && SSE_REG_P (operands[0])
+   && (!EXT_REX_SSE_REG_P (operands[0])
+       || TARGET_AVX512VL)"
   [(const_int 0)]
 {
   const machine_mode vmode = <MODEF:ssevecmode>mode;

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 9b7009ace6b317209b4fc2d70c4db42778e88727..c61098d9225b788713e3a2217185ebc2fc0bd658 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -4258,11 +4258,11 @@
    (set_attr "mode" "TI")])
 
 (define_insn "sse2_cvtsi2sd"
-  [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
+  [(set (match_operand:V2DF 0 "register_operand" "=x,x,v")
        (vec_merge:V2DF
          (vec_duplicate:V2DF
            (float:DF (match_operand:SI 2 "nonimmediate_operand" "r,m,rm")))
-         (match_operand:V2DF 1 "register_operand" "0,0,x")
+         (match_operand:V2DF 1 "register_operand" "0,0,v")
          (const_int 1)))]
   "TARGET_SSE2"
   "@
@@ -4275,7 +4275,7 @@
    (set_attr "amdfam10_decode" "vector,double,*")
    (set_attr "bdver1_decode" "double,direct,*")
    (set_attr "btver2_decode" "double,double,double")
-   (set_attr "prefix" "orig,orig,vex")
+   (set_attr "prefix" "orig,orig,maybe_evex")
    (set_attr "mode" "DF")])
 
 (define_insn "sse2_cvtsi2sdq<round_name>"

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6af4f3d71cb122b87e79d878a3b8f266bd30af33..db07b665ba75668f7672941a5b4faad37327f096 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2015-05-05  Ilya Tocar  <ilya.tocar@intel.com>
+
+       PR target/65915
+       * gcc.target/i386/pr65915.c: New.
+
 2015-05-05  Tom de Vries  <tom@codesourcery.com>
 
        * gcc.dg/tree-ssa/stdarg-2.c: Xfail f15 scans which test for presence of

diff --git a/gcc/testsuite/gcc.target/i386/pr65915.c b/gcc/testsuite/gcc.target/i386/pr65915.c
new file mode 100644 (file)
index 0000000..990c5aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr65915.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -fpic -mcmodel=medium" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target lp64 } */
+
+#include "avx512f-vrndscalepd-2.c"