(no commit message)
authorcolepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Wed, 4 Nov 2020 00:58:13 +0000 (00:58 +0000)
committerIkiWiki <ikiwiki.info>
Wed, 4 Nov 2020 00:58:13 +0000 (00:58 +0000)
HDL_workflow/ECP5_FPGA.mdwn

index ed72242ad91f0f76207944b04f2ee37c6fcf3b5f..d966dc567107e32a0a2bf4c5874ad3473146dd2f 100644 (file)
@@ -155,7 +155,7 @@ and therefore have no value are marked with 'NOT'
 
 ## Images of wires on FPGA and on STLINKV2
 
-[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg size="400x" ]]                                    
+[[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg size="200x" ]]                                    
 
 ## Questions