Fixed generation of temp names in verilog backend
authorClifford Wolf <clifford@clifford.at>
Fri, 7 Nov 2014 13:40:06 +0000 (14:40 +0100)
committerClifford Wolf <clifford@clifford.at>
Fri, 7 Nov 2014 13:40:06 +0000 (14:40 +0100)
backends/verilog/verilog_backend.cc

index 814c87be7e0bfec2b0af1a1500ad2e3e4a626a7d..7d08cc4e0196ec4cd44688aca49cd9d351ca6c0f 100644 (file)
@@ -51,16 +51,17 @@ void reset_auto_counter_id(RTLIL::IdString id, bool may_rename)
        if (*str == '$' && may_rename && !norename)
                auto_name_map[id] = auto_name_counter++;
 
-       if (str[0] != '_' && str[1] != 0)
+       if (str[0] != '\\' || str[1] != '_' || str[2] == 0)
                return;
-       for (int i = 0; str[i] != 0; i++) {
-               if (str[i] == '_')
+
+       for (int i = 2; str[i] != 0; i++) {
+               if (str[i] == '_' && str[i+1] == 0)
                        continue;
                if (str[i] < '0' || str[i] > '9')
                        return;
        }
 
-       int num = atoi(str+1);
+       int num = atoi(str+2);
        if (num >= auto_name_offset)
                auto_name_offset = num + 1;
 }