scons: Add missing override to appease clang

Make clang happy...again.

diff --git a/src/arch/hsail/insts/branch.hh b/src/arch/hsail/insts/branch.hh
index 54ad9a0426f92e93113fe61eba83974dbd3a203c..f4b00fc8d2b1f4292e0bd06c0e824d978b6d2ba6 100644 (file)
--- a/src/arch/hsail/insts/branch.hh
+++ b/src/arch/hsail/insts/branch.hh
@@ -51,7 +51,7 @@ namespace HsailISA
     class BrnInstBase : public HsailGPUStaticInst
     {
     public:
-        void generateDisassembly();
+        void generateDisassembly() override;
 
         Brig::BrigWidth8_t width;
         TargetType target;
@@ -69,43 +69,43 @@ namespace HsailISA
         uint32_t getTargetPc()  override { return target.getTarget(0, 0); }
 
         bool unconditionalJumpInstruction() override { return true; }
-        bool isVectorRegister(int operandIndex) {
+        bool isVectorRegister(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return target.isVectorRegister();
         }
-        bool isCondRegister(int operandIndex) {
+        bool isCondRegister(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return target.isCondRegister();
         }
-        bool isScalarRegister(int operandIndex) {
+        bool isScalarRegister(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return target.isScalarRegister();
         }
 
-        bool isSrcOperand(int operandIndex) {
+        bool isSrcOperand(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return true;
         }
 
-        bool isDstOperand(int operandIndex) {
+        bool isDstOperand(int operandIndex) override {
             return false;
         }
 
-        int getOperandSize(int operandIndex) {
+        int getOperandSize(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return target.opSize();
         }
 
-        int getRegisterIndex(int operandIndex) {
+        int getRegisterIndex(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return target.regIndex();
         }
 
-        int getNumOperands() {
+        int getNumOperands() override {
             return 1;
         }
 
-        void execute(GPUDynInstPtr gpuDynInst);
+        void execute(GPUDynInstPtr gpuDynInst) override;
     };
 
     template<typename TargetType>
@@ -166,7 +166,7 @@ namespace HsailISA
     class CbrInstBase : public HsailGPUStaticInst
     {
       public:
-        void generateDisassembly();
+        void generateDisassembly() override;
 
         Brig::BrigWidth8_t width;
         CRegOperand cond;
@@ -186,47 +186,47 @@ namespace HsailISA
 
         uint32_t getTargetPc() override { return target.getTarget(0, 0); }
 
-        void execute(GPUDynInstPtr gpuDynInst);
+        void execute(GPUDynInstPtr gpuDynInst) override;
         // Assumption: Target is operand 0, Condition Register is operand 1
-        bool isVectorRegister(int operandIndex) {
+        bool isVectorRegister(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             if (!operandIndex)
                 return target.isVectorRegister();
             else
                 return false;
         }
-        bool isCondRegister(int operandIndex) {
+        bool isCondRegister(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             if (!operandIndex)
                 return target.isCondRegister();
             else
                 return true;
         }
-        bool isScalarRegister(int operandIndex) {
+        bool isScalarRegister(int operandIndex) override {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if (!operandIndex)
                 return target.isScalarRegister();
             else
                 return false;
         }
-        bool isSrcOperand(int operandIndex) {
+        bool isSrcOperand(int operandIndex) override {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if (operandIndex == 0)
                 return true;
             return false;
         }
         // both Condition Register and Target are source operands
-        bool isDstOperand(int operandIndex) {
+        bool isDstOperand(int operandIndex) override {
             return false;
         }
-        int getOperandSize(int operandIndex) {
+        int getOperandSize(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             if (!operandIndex)
                 return target.opSize();
             else
                 return 1;
         }
-        int getRegisterIndex(int operandIndex) {
+        int getRegisterIndex(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             if (!operandIndex)
                 return target.regIndex();
@@ -235,7 +235,7 @@ namespace HsailISA
          }
 
         // Operands = Target, Condition Register
-        int getNumOperands() {
+        int getNumOperands() override {
             return 2;
         }
     };
@@ -335,7 +335,7 @@ namespace HsailISA
     class BrInstBase : public HsailGPUStaticInst
     {
       public:
-        void generateDisassembly();
+        void generateDisassembly() override;
 
         ImmOperand<uint32_t> width;
         TargetType target;
@@ -354,33 +354,33 @@ namespace HsailISA
 
         bool unconditionalJumpInstruction() override { return true; }
 
-        void execute(GPUDynInstPtr gpuDynInst);
-        bool isVectorRegister(int operandIndex) {
+        void execute(GPUDynInstPtr gpuDynInst) override;
+        bool isVectorRegister(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return target.isVectorRegister();
         }
-        bool isCondRegister(int operandIndex) {
+        bool isCondRegister(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return target.isCondRegister();
         }
-        bool isScalarRegister(int operandIndex) {
+        bool isScalarRegister(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return target.isScalarRegister();
         }
-        bool isSrcOperand(int operandIndex) {
+        bool isSrcOperand(int operandIndex) override {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return true;
         }
-        bool isDstOperand(int operandIndex) { return false; }
-        int getOperandSize(int operandIndex) {
+        bool isDstOperand(int operandIndex) override { return false; }
+        int getOperandSize(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return target.opSize();
         }
-        int getRegisterIndex(int operandIndex) {
+        int getRegisterIndex(int operandIndex) override {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return target.regIndex();
         }
-        int getNumOperands() { return 1; }
+        int getNumOperands() override { return 1; }
     };
 
     template<typename TargetType>

diff --git a/src/arch/hsail/insts/mem.hh b/src/arch/hsail/insts/mem.hh
index c3b3bd4f96dcd6adca38c2a626d6b599ceef0a5c..29091f9d141e2f9bbfb300e3a25d928550dec3a7 100644 (file)
--- a/src/arch/hsail/insts/mem.hh
+++ b/src/arch/hsail/insts/mem.hh
@@ -102,50 +102,52 @@ namespace HsailISA
             addr.init(op_offs, obj);
         }
 
-        int numSrcRegOperands() { return(this->addr.isVectorRegister()); }
-        int numDstRegOperands() { return dest.isVectorRegister(); }
-        bool isVectorRegister(int operandIndex)
+        int numSrcRegOperands() override
+        { return(this->addr.isVectorRegister()); }
+        int numDstRegOperands() override
+        { return dest.isVectorRegister(); }
+        bool isVectorRegister(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return((operandIndex == 0) ? dest.isVectorRegister() :
                    this->addr.isVectorRegister());
         }
-        bool isCondRegister(int operandIndex)
+        bool isCondRegister(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return((operandIndex == 0) ? dest.isCondRegister() :
                    this->addr.isCondRegister());
         }
-        bool isScalarRegister(int operandIndex)
+        bool isScalarRegister(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return((operandIndex == 0) ? dest.isScalarRegister() :
                    this->addr.isScalarRegister());
         }
-        bool isSrcOperand(int operandIndex)
+        bool isSrcOperand(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if (operandIndex > 0)
                 return(this->addr.isVectorRegister());
             return false;
         }
-        bool isDstOperand(int operandIndex) {
+        bool isDstOperand(int operandIndex) override {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return(operandIndex == 0);
         }
-        int getOperandSize(int operandIndex)
+        int getOperandSize(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return((operandIndex == 0) ? dest.opSize() :
                    this->addr.opSize());
         }
-        int getRegisterIndex(int operandIndex)
+        int getRegisterIndex(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return((operandIndex == 0) ? dest.regIndex() :
                    this->addr.regIndex());
         }
-        int getNumOperands()
+        int getNumOperands() override
         {
             if (this->addr.isVectorRegister())
                 return 2;
@@ -348,52 +350,53 @@ namespace HsailISA
             }
         }
 
-        int numSrcRegOperands() { return(this->addr.isVectorRegister()); }
-        int numDstRegOperands() { return dest.isVectorRegister(); }
-        int getNumOperands()
+        int numSrcRegOperands() override
+        { return(this->addr.isVectorRegister()); }
+        int numDstRegOperands() override { return dest.isVectorRegister(); }
+        int getNumOperands() override
         {
             if (this->addr.isVectorRegister())
                 return 2;
             else
                 return 1;
         }
-        bool isVectorRegister(int operandIndex)
+        bool isVectorRegister(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return((operandIndex == 0) ? dest.isVectorRegister() :
                    this->addr.isVectorRegister());
         }
-        bool isCondRegister(int operandIndex)
+        bool isCondRegister(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return((operandIndex == 0) ? dest.isCondRegister() :
                    this->addr.isCondRegister());
         }
-        bool isScalarRegister(int operandIndex)
+        bool isScalarRegister(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return((operandIndex == 0) ? dest.isScalarRegister() :
                    this->addr.isScalarRegister());
         }
-        bool isSrcOperand(int operandIndex)
+        bool isSrcOperand(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if (operandIndex > 0)
                 return(this->addr.isVectorRegister());
             return false;
         }
-        bool isDstOperand(int operandIndex)
+        bool isDstOperand(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return(operandIndex == 0);
         }
-        int getOperandSize(int operandIndex)
+        int getOperandSize(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return((operandIndex == 0) ? dest.opSize() :
                    this->addr.opSize());
         }
-        int getRegisterIndex(int operandIndex)
+        int getRegisterIndex(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return((operandIndex == 0) ? dest.regIndex() :
@@ -410,7 +413,7 @@ namespace HsailISA
     {
         typename DestDataType::OperandType::DestOperand dest_vect[4];
         uint16_t num_dest_operands;
-        void generateDisassembly();
+        void generateDisassembly() override;
 
       public:
         LdInst(const Brig::BrigInstBase *ib, const BrigObject *obj,
@@ -539,7 +542,7 @@ namespace HsailISA
             return this->segment == Brig::BRIG_SEGMENT_GROUP;
         }
 
-        bool isVectorRegister(int operandIndex)
+        bool isVectorRegister(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if ((num_dest_operands != getNumOperands()) &&
@@ -555,7 +558,7 @@ namespace HsailISA
             }
             return false;
         }
-        bool isCondRegister(int operandIndex)
+        bool isCondRegister(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if ((num_dest_operands != getNumOperands()) &&
@@ -569,7 +572,7 @@ namespace HsailISA
                        AddrOperandType>::dest.isCondRegister();
             return false;
         }
-        bool isScalarRegister(int operandIndex)
+        bool isScalarRegister(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if ((num_dest_operands != getNumOperands()) &&
@@ -583,7 +586,7 @@ namespace HsailISA
                        AddrOperandType>::dest.isScalarRegister();
             return false;
         }
-        bool isSrcOperand(int operandIndex)
+        bool isSrcOperand(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if ((num_dest_operands != getNumOperands()) &&
@@ -591,7 +594,7 @@ namespace HsailISA
                 return(this->addr.isVectorRegister());
             return false;
         }
-        bool isDstOperand(int operandIndex)
+        bool isDstOperand(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if ((num_dest_operands != getNumOperands()) &&
@@ -599,7 +602,7 @@ namespace HsailISA
                 return false;
             return true;
         }
-        int getOperandSize(int operandIndex)
+        int getOperandSize(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if ((num_dest_operands != getNumOperands()) &&
@@ -613,7 +616,7 @@ namespace HsailISA
                        AddrOperandType>::dest.opSize());
             return 0;
         }
-        int getRegisterIndex(int operandIndex)
+        int getRegisterIndex(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if ((num_dest_operands != getNumOperands()) &&
@@ -627,14 +630,14 @@ namespace HsailISA
                        AddrOperandType>::dest.regIndex());
             return -1;
         }
-        int getNumOperands()
+        int getNumOperands() override
         {
             if (this->addr.isVectorRegister() || this->addr.isScalarRegister())
                 return(num_dest_operands+1);
             else
                 return(num_dest_operands);
         }
-        void execute(GPUDynInstPtr gpuDynInst);
+        void execute(GPUDynInstPtr gpuDynInst) override;
     };
 
     template<typename MemDT, typename DestDT>
@@ -851,48 +854,48 @@ namespace HsailISA
             }
         }
 
-        int numDstRegOperands() { return 0; }
-        int numSrcRegOperands()
+        int numDstRegOperands() override { return 0; }
+        int numSrcRegOperands() override
         {
             return src.isVectorRegister() + this->addr.isVectorRegister();
         }
-        int getNumOperands()
+        int getNumOperands() override
         {
             if (this->addr.isVectorRegister() || this->addr.isScalarRegister())
                 return 2;
             else
                 return 1;
         }
-        bool isVectorRegister(int operandIndex)
+        bool isVectorRegister(int operandIndex) override
         {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return !operandIndex ? src.isVectorRegister() :
                    this->addr.isVectorRegister();
         }
-        bool isCondRegister(int operandIndex)
+        bool isCondRegister(int operandIndex) override
         {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return !operandIndex ? src.isCondRegister() :
                    this->addr.isCondRegister();
         }
-        bool isScalarRegister(int operandIndex)
+        bool isScalarRegister(int operandIndex) override
         {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return !operandIndex ? src.isScalarRegister() :
                    this->addr.isScalarRegister();
         }
-        bool isSrcOperand(int operandIndex)
+        bool isSrcOperand(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return true;
         }
-        bool isDstOperand(int operandIndex) { return false; }
-        int getOperandSize(int operandIndex)
+        bool isDstOperand(int operandIndex) override { return false; }
+        int getOperandSize(int operandIndex) override
         {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return !operandIndex ? src.opSize() : this->addr.opSize();
         }
-        int getRegisterIndex(int operandIndex)
+        int getRegisterIndex(int operandIndex) override
         {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return !operandIndex ? src.regIndex() : this->addr.regIndex();
@@ -910,7 +913,7 @@ namespace HsailISA
       public:
         typename SrcDataType::OperandType::SrcOperand src_vect[4];
         uint16_t num_src_operands;
-        void generateDisassembly();
+        void generateDisassembly() override;
 
         StInst(const Brig::BrigInstBase *ib, const BrigObject *obj,
                         const char *_opcode, int srcIdx)
@@ -1045,7 +1048,7 @@ namespace HsailISA
         }
 
       public:
-        bool isVectorRegister(int operandIndex)
+        bool isVectorRegister(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if (operandIndex == num_src_operands)
@@ -1058,7 +1061,7 @@ namespace HsailISA
                        AddrOperandType>::src.isVectorRegister();
             return false;
         }
-        bool isCondRegister(int operandIndex)
+        bool isCondRegister(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if (operandIndex == num_src_operands)
@@ -1071,7 +1074,7 @@ namespace HsailISA
                        AddrOperandType>::src.isCondRegister();
             return false;
         }
-        bool isScalarRegister(int operandIndex)
+        bool isScalarRegister(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if (operandIndex == num_src_operands)
@@ -1084,13 +1087,13 @@ namespace HsailISA
                        AddrOperandType>::src.isScalarRegister();
             return false;
         }
-        bool isSrcOperand(int operandIndex)
+        bool isSrcOperand(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return true;
         }
-        bool isDstOperand(int operandIndex) { return false; }
-        int getOperandSize(int operandIndex)
+        bool isDstOperand(int operandIndex) override { return false; }
+        int getOperandSize(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if (operandIndex == num_src_operands)
@@ -1103,7 +1106,7 @@ namespace HsailISA
                        AddrOperandType>::src.opSize();
             return 0;
         }
-        int getRegisterIndex(int operandIndex)
+        int getRegisterIndex(int operandIndex) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if (operandIndex == num_src_operands)
@@ -1116,14 +1119,14 @@ namespace HsailISA
                        AddrOperandType>::src.regIndex();
             return -1;
         }
-        int getNumOperands()
+        int getNumOperands() override
         {
             if (this->addr.isVectorRegister() || this->addr.isScalarRegister())
                 return num_src_operands + 1;
             else
                 return num_src_operands;
         }
-        void execute(GPUDynInstPtr gpuDynInst);
+        void execute(GPUDynInstPtr gpuDynInst) override;
     };
 
     template<typename DataType, typename SrcDataType>
@@ -1332,7 +1335,7 @@ namespace HsailISA
         public MemInst
     {
       public:
-        void generateDisassembly();
+        void generateDisassembly() override;
 
         AtomicInst(const Brig::BrigInstBase *ib, const BrigObject *obj,
                    const char *_opcode)
@@ -1376,7 +1379,7 @@ namespace HsailISA
 
         }
 
-        void execute(GPUDynInstPtr gpuDynInst);
+        void execute(GPUDynInstPtr gpuDynInst) override;
 
         bool
         isLocalMem() const override

diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index a2f356e1f0443bf60cd3c2db69686ad92dd1a01a..af9183192339f9a058711f8323eb4ac00e6743e9 100644 (file)
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -87,7 +87,7 @@ class TLB : public BaseTLB
     MipsISA::PTE *getEntry(unsigned) const;
     virtual ~TLB();
 
-    void takeOverFrom(BaseTLB *otlb) {}
+    void takeOverFrom(BaseTLB *otlb) override {}
 
     int smallPages;
     int getsize() const { return size; }
@@ -95,8 +95,8 @@ class TLB : public BaseTLB
     MipsISA::PTE &index(bool advance = true);
     void insert(Addr vaddr, MipsISA::PTE &pte);
     void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
-    void flushAll();
-    void demapPage(Addr vaddr, uint64_t asn)
+    void flushAll() override;
+    void demapPage(Addr vaddr, uint64_t asn) override
     {
         panic("demapPage unimplemented.\n");
     }
@@ -110,7 +110,7 @@ class TLB : public BaseTLB
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;
 
-    void regStats();
+    void regStats() override;
 
     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
     void translateTiming(RequestPtr req, ThreadContext *tc,

diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index 81ea22cc4bbab091d276f5babfec1110df51a812..de03da034545057af9786449a73a289193507b22 100644 (file)
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -133,7 +133,7 @@ class TLB : public BaseTLB
     TLB(const Params *p);
     virtual ~TLB();
 
-    void takeOverFrom(BaseTLB *otlb) {}
+    void takeOverFrom(BaseTLB *otlb) override {}
 
     int probeEntry(Addr vpn,uint8_t) const;
     PowerISA::PTE *getEntry(unsigned) const;
@@ -149,10 +149,10 @@ class TLB : public BaseTLB
     PowerISA::PTE &index(bool advance = true);
     void insert(Addr vaddr, PowerISA::PTE &pte);
     void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages);
-    void flushAll();
+    void flushAll() override;
 
     void
-    demapPage(Addr vaddr, uint64_t asn)
+    demapPage(Addr vaddr, uint64_t asn) override
     {
         panic("demapPage unimplemented.\n");
     }
@@ -175,7 +175,7 @@ class TLB : public BaseTLB
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;
 
-    void regStats();
+    void regStats() override;
 };
 
 } // namespace PowerISA

diff --git a/src/arch/sparc/system.hh b/src/arch/sparc/system.hh
index d4b61bd9534b60e684c7e7f71fa96262572dc122..ac877a9646ace58b920a9347a85227f176ae879a 100644 (file)
--- a/src/arch/sparc/system.hh
+++ b/src/arch/sparc/system.hh
@@ -123,8 +123,8 @@ class SparcSystem : public System
         return addFuncEvent<T>(openbootSymtab, lbl);
     }
 
-    virtual Addr
-    fixFuncEventAddr(Addr addr)
+    Addr
+    fixFuncEventAddr(Addr addr) override
     {
         //XXX This may eventually have to do something useful.
         return addr;

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index c77f964c0e43fb11e56cc7b0893a0d54247e4966..93ab9defd4e46f9b8fcc993be56d7ac0d7b1f5ba 100644 (file)
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -328,13 +328,13 @@ class CheckerCPU : public BaseCPU, public ExecContext
     }
 
 #if THE_ISA == MIPS_ISA
-    MiscReg readRegOtherThread(int misc_reg, ThreadID tid)
+    MiscReg readRegOtherThread(int misc_reg, ThreadID tid) override
     {
         panic("MIPS MT not defined for CheckerCPU.\n");
         return 0;
     }
 
-    void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid)
+    void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) override
     {
         panic("MIPS MT not defined for CheckerCPU.\n");
     }

diff --git a/src/dev/mips/malta.hh b/src/dev/mips/malta.hh
index 205abce2706336d838947a9042f45482be55bde9..de2e8617ca80a2521218d1209f0a593e76798c93 100755 (executable)
--- a/src/dev/mips/malta.hh
+++ b/src/dev/mips/malta.hh
@@ -87,22 +87,22 @@ class Malta : public Platform
     /**
      * Cause the cpu to post a serial interrupt to the CPU.
      */
-    virtual void postConsoleInt();
+    void postConsoleInt() override;
 
     /**
      * Clear a posted CPU interrupt (id=55)
      */
-    virtual void clearConsoleInt();
+    void clearConsoleInt() override;
 
     /**
      * Cause the chipset to post a cpi interrupt to the CPU.
      */
-    virtual void postPciInt(int line);
+    void postPciInt(int line) override;
 
     /**
      * Clear a posted PCI->CPU interrupt
      */
-    virtual void clearPciInt(int line);
+    void clearPciInt(int line) override;
 
 
     virtual Addr pciToDma(Addr pciAddr) const;

diff --git a/src/dev/mips/malta_cchip.hh b/src/dev/mips/malta_cchip.hh
index 5f8baad819694ac950e5b676b1bce9b781fbcc26..150641878d67e13f73fcc4a8d8c49a80e1c83a43 100755 (executable)
--- a/src/dev/mips/malta_cchip.hh
+++ b/src/dev/mips/malta_cchip.hh
@@ -94,9 +94,9 @@ class MaltaCChip : public BasicPioDevice
      */
     MaltaCChip(Params *p);
 
-    virtual Tick read(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
 
-    virtual Tick write(PacketPtr pkt);
+    Tick write(PacketPtr pkt) override;
 
     /**
      * post an RTC interrupt to the CPU

diff --git a/src/dev/mips/malta_io.hh b/src/dev/mips/malta_io.hh
index f6fdfa53b45dd7793f015df5edd390188dcac219..8b224a9420ea1ad71445da2ab7ede53924a5b1da 100755 (executable)
--- a/src/dev/mips/malta_io.hh
+++ b/src/dev/mips/malta_io.hh
@@ -120,8 +120,8 @@ class MaltaIO : public BasicPioDevice
      */
     MaltaIO(const Params *p);
 
-    virtual Tick read(PacketPtr pkt);
-    virtual Tick write(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
+    Tick write(PacketPtr pkt) override;
 
 
     /** Post an Interrupt to the CPU */
@@ -136,7 +136,7 @@ class MaltaIO : public BasicPioDevice
     /**
      * Start running.
      */
-    virtual void startup();
+    void startup() override;
 
 };
 

diff --git a/src/dev/sparc/dtod.hh b/src/dev/sparc/dtod.hh
index 98208a9922ee325910de173afb8aa4a0ead091a2..1fcc70a3b81aa1bcea339dcf3fddd8fb6f01d1df 100644 (file)
--- a/src/dev/sparc/dtod.hh
+++ b/src/dev/sparc/dtod.hh
@@ -60,8 +60,8 @@ class DumbTOD : public BasicPioDevice
         return dynamic_cast<const Params *>(_params);
     }
 
-    virtual Tick read(PacketPtr pkt);
-    virtual Tick write(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
+    Tick write(PacketPtr pkt) override;
 
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;

diff --git a/src/dev/sparc/iob.hh b/src/dev/sparc/iob.hh
index 1de625eba8bf0627beea794ce3a969f6fb69c458..d62c8e6710b2878c24844362790413c1f5e19c2e 100644 (file)
--- a/src/dev/sparc/iob.hh
+++ b/src/dev/sparc/iob.hh
@@ -132,14 +132,14 @@ class Iob : public PioDevice
         return dynamic_cast<const Params *>(_params);
     }
 
-    virtual Tick read(PacketPtr pkt);
-    virtual Tick write(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
+    Tick write(PacketPtr pkt) override;
     void generateIpi(Type type, int cpu_id, int vector);
     void receiveDeviceInterrupt(DeviceId devid);
     bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
                               uint64_t d1);
 
-    AddrRangeList getAddrRanges() const;
+    AddrRangeList getAddrRanges() const override;
 
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;

diff --git a/src/dev/sparc/mm_disk.hh b/src/dev/sparc/mm_disk.hh
index 2d551fe3fe4a40a26fb44e7d793779529077c462..8572d5329b2679cb5d642e5d8925ec49cd7970be 100644 (file)
--- a/src/dev/sparc/mm_disk.hh
+++ b/src/dev/sparc/mm_disk.hh
@@ -58,8 +58,8 @@ class MmDisk : public BasicPioDevice
         return dynamic_cast<const Params *>(_params);
     }
 
-    virtual Tick read(PacketPtr pkt);
-    virtual Tick write(PacketPtr pkt);
+    Tick read(PacketPtr pkt) override;
+    Tick write(PacketPtr pkt) override;
 
     void serialize(CheckpointOut &cp) const override;
 };

diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index 9cf187c8323e59fa194da87d505a74f3ac4390d0..3b408e5ac9da0136c0bb650c003566aeb9b23346 100644 (file)
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -56,11 +56,11 @@ class DMASequencer : public RubyPort
     void init() override;
 
     /* external interface */
-    RequestStatus makeRequest(PacketPtr pkt);
+    RequestStatus makeRequest(PacketPtr pkt) override;
     bool busy() { return m_is_busy;}
-    int outstandingCount() const { return (m_is_busy ? 1 : 0); }
-    bool isDeadlockEventScheduled() const { return false; }
-    void descheduleDeadlockEvent() {}
+    int outstandingCount() const override { return (m_is_busy ? 1 : 0); }
+    bool isDeadlockEventScheduled() const override { return false; }
+    void descheduleDeadlockEvent() override {}
 
     /* SLICC callback */
     void dataCallback(const DataBlock & dblk);