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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 236abd5a0558821afe126178ad362d4ad659ac26..4e31821445d24cfdedcbaf73cffcb413d74e8342 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -658,7 +658,11 @@ Thus the new VL comprises a contiguous vector of results,
 all of which pass the testing criteria (equal to zero, less than zero).
 
 The CR-based data-driven fail-on-first is new and not found in ARM
-SVE or RVV. It is extremely useful for reducing instruction count,
+SVE or RVV. At the same time it is also "old" because it is a generalisation
+of the Z80
+[Block compare](https://rvbelzen.tripod.com/z80prgtemp/z80prg04.htm)
+instructions, especially 
+ It is extremely useful for reducing instruction count,
 however requires speculative execution involving modifications of VL
 to get high performance implementations.  An additional mode (RC1=1)
 effectively turns what would otherwise be an arithmetic operation