re PR target/64205 (powerpc64-linux --with-cpu=G5 bootstrap failure)

[gcc]
2015-02-06  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/64205
	* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Do not
	add a general secondary reload handler for SDmode, unless we have
	both read/write support for SDmode.

[gcc/testsuite]
2015-02-06  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/64205
	* gcc.target/powerpc/pr64205.c: New file.

From-SVN: r220485

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 59ed4b2e74124ac2fc677106447bb3eb79098361..7b9d630b85d31bddcb7ee8cab0580d5582834556 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2015-02-06  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/64205
+       * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Do not
+       add a general secondary reload handler for SDmode, unless we have
+       both read/write support for SDmode.
+
 2015-02-06  Jakub Jelinek  <jakub@redhat.com>
 
        PR middle-end/64937
@@ -23,7 +30,7 @@
        (h8300_push_pop): Corresponding changes.
        (h8300_expand_prologue): Likewise.
        (h8300_swap_into_er6): Likewise.  Do not set RTX_FRAME_RELATED_P.
-               
+
 2015-02-06  Jakub Jelinek  <jakub@redhat.com>
 
        PR rtl-optimization/64957

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 4f88328a506351de8947affc744f498734039e60..949c4d22b21cb91d681e61ba1570b531493becb1 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2849,8 +2849,14 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
          reg_addr[DDmode].reload_load     = CODE_FOR_reload_dd_di_load;
          reg_addr[SFmode].reload_store    = CODE_FOR_reload_sf_di_store;
          reg_addr[SFmode].reload_load     = CODE_FOR_reload_sf_di_load;
-         reg_addr[SDmode].reload_store    = CODE_FOR_reload_sd_di_store;
-         reg_addr[SDmode].reload_load     = CODE_FOR_reload_sd_di_load;
+
+         /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
+            available.  */
+         if (TARGET_NO_SDMODE_STACK)
+           {
+             reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
+             reg_addr[SDmode].reload_load  = CODE_FOR_reload_sd_di_load;
+           }
 
          if (TARGET_VSX_TIMODE)
            {
@@ -2903,8 +2909,14 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
          reg_addr[DDmode].reload_load     = CODE_FOR_reload_dd_si_load;
          reg_addr[SFmode].reload_store    = CODE_FOR_reload_sf_si_store;
          reg_addr[SFmode].reload_load     = CODE_FOR_reload_sf_si_load;
-         reg_addr[SDmode].reload_store    = CODE_FOR_reload_sd_si_store;
-         reg_addr[SDmode].reload_load     = CODE_FOR_reload_sd_si_load;
+
+         /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
+            available.  */
+         if (TARGET_NO_SDMODE_STACK)
+           {
+             reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
+             reg_addr[SDmode].reload_load  = CODE_FOR_reload_sd_si_load;
+           }
 
          if (TARGET_VSX_TIMODE)
            {

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 36c49f7b3922c10e7d86c924ac370fc8348385ae..e3e54449232468d78eb1cf9c06420082aebf8275 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2015-02-06  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/64205
+       * gcc.target/powerpc/pr64205.c: New file.
+
 2015-02-06  Uros Bizjak  <ubizjak@gmail.com>
 
        * gcc.target/i386/pr64317.c: Compile for 32bit *-*-linux* targets.

diff --git a/gcc/testsuite/gcc.target/powerpc/pr64205.c b/gcc/testsuite/gcc.target/powerpc/pr64205.c
new file mode 100644 (file)
index 0000000..58e4b98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr64205.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=G5" } } */
+/* { dg-options "-O2 -mcpu=G5 -maltivec -m32" } */
+
+union ieee754r_Decimal32
+{
+  _Decimal32 sd;
+  unsigned int cc0;
+};
+
+unsigned int
+__decoded32 (_Decimal32 a)
+{
+    union ieee754r_Decimal32 d;
+    d.sd = a;
+    return d.cc0;
+}