gallium/radeon: make r600_gfx_write_fence more generic
authorMarek Olšák <marek.olsak@amd.com>
Mon, 3 Oct 2016 13:32:36 +0000 (15:32 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Wed, 26 Oct 2016 11:02:58 +0000 (13:02 +0200)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/gallium/drivers/radeon/r600_pipe_common.c
src/gallium/drivers/radeon/r600_pipe_common.h
src/gallium/drivers/radeon/r600_query.c
src/gallium/drivers/radeonsi/si_perfcounter.c

index c4b70dc6089dd8a372cb20b4508364520705b560..835008360a6de253f34840fe1bb6ddbcbb67fc01 100644 (file)
@@ -80,10 +80,27 @@ void radeon_shader_binary_clean(struct radeon_shader_binary *b)
  * pipe_context
  */
 
-void r600_gfx_write_fence(struct r600_common_context *ctx, struct r600_resource *buf,
-                         uint64_t va, uint32_t old_value, uint32_t new_value)
+/**
+ * Write an EOP event.
+ *
+ * \param event                EVENT_TYPE_*
+ * \param event_flags  Optional cache flush flags (TC)
+ * \param data_sel     1 = fence, 3 = timestamp
+ * \param buf          Buffer
+ * \param va           GPU address
+ * \param old_value    Previous fence value (for a bug workaround)
+ * \param new_value    Fence value to write for this event.
+ */
+void r600_gfx_write_event_eop(struct r600_common_context *ctx,
+                             unsigned event, unsigned event_flags,
+                             unsigned data_sel,
+                             struct r600_resource *buf, uint64_t va,
+                             uint32_t old_fence, uint32_t new_fence)
 {
        struct radeon_winsys_cs *cs = ctx->gfx.cs;
+       unsigned op = EVENT_TYPE(event) |
+                     EVENT_INDEX(5) |
+                     event_flags;
 
        if (ctx->chip_class == CIK) {
                /* Two EOP events are required to make all engines go idle
@@ -91,20 +108,18 @@ void r600_gfx_write_fence(struct r600_common_context *ctx, struct r600_resource
                 * is written.
                 */
                radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-               radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
-                               EVENT_INDEX(5));
+               radeon_emit(cs, op);
                radeon_emit(cs, va);
-               radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(1));
-               radeon_emit(cs, old_value); /* immediate data */
+               radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
+               radeon_emit(cs, old_fence); /* immediate data */
                radeon_emit(cs, 0); /* unused */
        }
 
        radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-       radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
-                       EVENT_INDEX(5));
+       radeon_emit(cs, op);
        radeon_emit(cs, va);
-       radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(1));
-       radeon_emit(cs, new_value); /* immediate data */
+       radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
+       radeon_emit(cs, new_fence); /* immediate data */
        radeon_emit(cs, 0); /* unused */
 
        r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
index 5cfcad688c4bb694b192dccc0d65d6bfbcbb2da3..170037187b516f6c90ba0338de7f106386867615 100644 (file)
@@ -705,8 +705,11 @@ r600_invalidate_resource(struct pipe_context *ctx,
                         struct pipe_resource *resource);
 
 /* r600_common_pipe.c */
-void r600_gfx_write_fence(struct r600_common_context *ctx, struct r600_resource *buf,
-                         uint64_t va, uint32_t old_value, uint32_t new_value);
+void r600_gfx_write_event_eop(struct r600_common_context *ctx,
+                             unsigned event, unsigned event_flags,
+                             unsigned data_sel,
+                             struct r600_resource *buf, uint64_t va,
+                             uint32_t old_fence, uint32_t new_fence);
 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
 void r600_gfx_wait_fence(struct r600_common_context *ctx,
                         uint64_t va, uint32_t ref, uint32_t mask);
index 91385ae9820ef21a28a2ec4edcfd9ba830adc26e..ac71a4358e0ede71fa89f232a5b2ee6b84e0d494 100644 (file)
@@ -671,7 +671,8 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
                        RADEON_PRIO_QUERY);
 
        if (fence_va)
-               r600_gfx_write_fence(ctx, query->buffer.buf, fence_va, 0, 0x80000000);
+               r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, 1,
+                                        query->buffer.buf, fence_va, 0, 0x80000000);
 }
 
 static void r600_query_hw_emit_stop(struct r600_common_context *ctx,
index 5e0bf3f9e1bdb53abf2d0094341566083192a47d..00db2c45badb1dee005b2e9add4a1dad5a19c1ab 100644 (file)
@@ -590,7 +590,8 @@ static void si_pc_emit_stop(struct r600_common_context *ctx,
 {
        struct radeon_winsys_cs *cs = ctx->gfx.cs;
 
-       r600_gfx_write_fence(ctx, buffer, va, 1, 0);
+       r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, 1,
+                                buffer, va, 1, 0);
        r600_gfx_wait_fence(ctx, va, 0, 0xffffffff);
 
        radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));