ISA: Set up common trace flags for tracing registers.

diff --git a/src/arch/SConscript b/src/arch/SConscript
index 932cf75099a7ccb6630f8a080dafdd3049b716b0..2b0af2816b8772d9014caa65ff3b860739bc98b8 100644 (file)
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -126,3 +126,8 @@ else:
                                emitter = isa_desc_emitter)
 
 env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
+
+TraceFlag('IntRegs')
+TraceFlag('FloatRegs')
+TraceFlag('MiscRegs')
+CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])

diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc
index e1b5ea7c8fe582225dda2277919442d0c710d87b..cf33b6a779f72bba8d96396bea0a5ecb85067398 100644 (file)
--- a/src/arch/sparc/floatregfile.cc
+++ b/src/arch/sparc/floatregfile.cc
@@ -75,7 +75,8 @@ FloatReg FloatRegFile::readReg(int floatReg, int width)
         result32 = htog(result32);
         memcpy(&fresult32, &result32, sizeof(result32));
         result = fresult32;
-        DPRINTF(Sparc, "Read FP32 register %d = [%f]0x%x\n", floatReg, result, result32);
+        DPRINTF(FloatRegs, "Read FP32 register %d = [%f]0x%x\n",
+                floatReg, result, result32);
         break;
       case DoubleWidth:
         uint64_t result64;
@@ -84,7 +85,8 @@ FloatReg FloatRegFile::readReg(int floatReg, int width)
         result64 = htog(result64);
         memcpy(&fresult64, &result64, sizeof(result64));
         result = fresult64;
-        DPRINTF(Sparc, "Read FP64 register %d = [%f]0x%x\n", floatReg, result, result64);
+        DPRINTF(FloatRegs, "Read FP64 register %d = [%f]0x%x\n",
+                floatReg, result, result64);
         break;
       case QuadWidth:
         panic("Quad width FP not implemented.");
@@ -107,13 +109,15 @@ FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
         uint32_t result32;
         memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
         result = htog(result32);
-        DPRINTF(Sparc, "Read FP32 bits register %d = 0x%x\n", floatReg, result);
+        DPRINTF(FloatRegs, "Read FP32 bits register %d = 0x%x\n",
+                floatReg, result);
         break;
       case DoubleWidth:
         uint64_t result64;
         memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
         result = htog(result64);
-        DPRINTF(Sparc, "Read FP64 bits register %d = 0x%x\n", floatReg, result);
+        DPRINTF(FloatRegs, "Read FP64 bits register %d = 0x%x\n",
+                floatReg, result);
         break;
       case QuadWidth:
         panic("Quad width FP not implemented.");
@@ -141,14 +145,16 @@ Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
         memcpy(&result32, &fresult32, sizeof(result32));
         result32 = gtoh(result32);
         memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
-        DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result32);
+        DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n",
+                floatReg, result32);
         break;
       case DoubleWidth:
         fresult64 = val;
         memcpy(&result64, &fresult64, sizeof(result64));
         result64 = gtoh(result64);
         memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
-        DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result64);
+        DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n",
+                floatReg, result64);
         break;
       case QuadWidth:
         panic("Quad width FP not implemented.");
@@ -171,12 +177,14 @@ Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width)
       case SingleWidth:
         result32 = gtoh((uint32_t)val);
         memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
-        DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result32);
+        DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n",
+                floatReg, result32);
         break;
       case DoubleWidth:
         result64 = gtoh((uint64_t)val);
         memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
-        DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result64);
+        DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n",
+                floatReg, result64);
         break;
       case QuadWidth:
         panic("Quad width FP not implemented.");

diff --git a/src/arch/sparc/intregfile.cc b/src/arch/sparc/intregfile.cc
index c111172a93f0f8c0f944f3802a17ff553e4ff851..7c20d5169694ec2781a7d90a1e7b3c752d174758 100644 (file)
--- a/src/arch/sparc/intregfile.cc
+++ b/src/arch/sparc/intregfile.cc
@@ -70,7 +70,7 @@ IntRegFile::IntRegFile()
 
 IntReg IntRegFile::readReg(int intReg)
 {
-    DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, regs[intReg]);
+    DPRINTF(IntRegs, "Read register %d = 0x%x\n", intReg, regs[intReg]);
     return regs[intReg];
     /* XXX Currently not used. When used again regView/offset need to be
      * serialized!
@@ -83,7 +83,7 @@ IntReg IntRegFile::readReg(int intReg)
         panic("Tried to read non-existant integer register %d, %d\n",
                 NumIntArchRegs + NumMicroIntRegs + intReg, intReg);
 
-    DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, val);
+    DPRINTF(IntRegs, "Read register %d = 0x%x\n", intReg, val);
     return val;
     */
 }
@@ -92,7 +92,7 @@ void IntRegFile::setReg(int intReg, const IntReg &val)
 {
     if(intReg)
     {
-        DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val);
+        DPRINTF(IntRegs, "Wrote register %d = 0x%x\n", intReg, val);
         regs[intReg] = val;
     }
     return;
@@ -100,7 +100,7 @@ void IntRegFile::setReg(int intReg, const IntReg &val)
      * serialized!
     if(intReg)
     {
-        DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val);
+        DPRINTF(IntRegs, "Wrote register %d = 0x%x\n", intReg, val);
         if(intReg < NumIntArchRegs)
             regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val;
         else if((intReg -= NumIntArchRegs) < NumMicroIntRegs)

diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index b22ceb657743b4133fad1eabfd46aab24f650ebf..e06d4b15a5b6ae5bfa2fe0d6d1fb01990e23c55c 100644 (file)
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -227,7 +227,7 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 
         /** Floating Point Status Register */
       case MISCREG_FSR:
-        DPRINTF(Sparc, "FSR read as: %#x\n", fsr);
+        DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr);
         return fsr;
 
       case MISCREG_MMU_P_CONTEXT:
@@ -446,7 +446,7 @@ void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
         /** Floating Point Status Register */
       case MISCREG_FSR:
         fsr = val;
-        DPRINTF(Sparc, "FSR written with: %#x\n", fsr);
+        DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr);
         break;
 
       case MISCREG_MMU_P_CONTEXT:

diff --git a/src/arch/x86/floatregfile.cc b/src/arch/x86/floatregfile.cc
index 1c49ea9c64ee7197ac84c9aebdedb6e57611fcf2..da5372c699a60a4ff0e884602e262b5feb9c5b44 100644 (file)
--- a/src/arch/x86/floatregfile.cc
+++ b/src/arch/x86/floatregfile.cc
@@ -113,27 +113,27 @@ void FloatRegFile::clear()
 FloatReg FloatRegFile::readReg(int floatReg, int width)
 {
     FloatReg reg = d[floatReg];
-    DPRINTF(X86, "Reading %f from register %d.\n", reg, floatReg);
+    DPRINTF(FloatRegs, "Reading %f from register %d.\n", reg, floatReg);
     return reg;
 }
 
 FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
 {
     FloatRegBits reg = q[floatReg];
-    DPRINTF(X86, "Reading %#x from register %d.\n", reg, floatReg);
+    DPRINTF(FloatRegs, "Reading %#x from register %d.\n", reg, floatReg);
     return reg;
 }
 
 Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
 {
-    DPRINTF(X86, "Writing %f to register %d.\n", val, floatReg);
+    DPRINTF(FloatRegs, "Writing %f to register %d.\n", val, floatReg);
     d[floatReg] = val;
     return NoFault;
 }
 
 Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width)
 {
-    DPRINTF(X86, "Writing bits %#x to register %d.\n", val, floatReg);
+    DPRINTF(FloatRegs, "Writing bits %#x to register %d.\n", val, floatReg);
     q[floatReg] = val;
     return NoFault;
 }

diff --git a/src/arch/x86/intregfile.cc b/src/arch/x86/intregfile.cc
index 9c9ea134e6f7182d228f5b9f20296d925f68e170..43cfb80829b9276970915e0c526959672c7cdf79 100644 (file)
--- a/src/arch/x86/intregfile.cc
+++ b/src/arch/x86/intregfile.cc
@@ -120,13 +120,15 @@ void IntRegFile::clear()
 
 IntReg IntRegFile::readReg(int intReg)
 {
-    DPRINTF(X86, "Read int reg %d and got value %#x\n", intReg, regs[intReg]);
+    DPRINTF(IntRegs, "Read int reg %d and got value %#x\n",
+            intReg, regs[intReg]);
     return regs[intReg];
 }
 
 void IntRegFile::setReg(int intReg, const IntReg &val)
 {
-    DPRINTF(X86, "Setting int reg %d to value %#x\n", intReg, val);
+    DPRINTF(IntRegs, "Setting int reg %d to value %#x\n",
+            intReg, val);
     regs[intReg] = val;
 }