--- /dev/null
+cd /benchmarks/bn
+./bottleneck-app
+m5 exit
Benchmarks['ValStreamScale'] = [Machine('micro_streamscale.rcS', '512MB')]
Benchmarks['ValStreamCopy'] = [Machine('micro_streamcopy.rcS', '512MB')]
+
+Benchmarks['bnAn'] = [Machine('/z/saidi/work/m5.newmem.head/configs/boot/bn-app.rcS', '128MB', '/z/saidi/work/bottleneck/bnimg.img')]
+
benchs = Benchmarks.keys()
benchs.sort()
DefinedBenchmarks = ", ".join(benchs)
# Base sources used by all configurations.
base_sources = Split('''
+ base/annotate.cc
base/circlebuf.cc
base/cprintf.cc
base/fast_alloc.cc
0x54: m5panic({{
panic("M5 panic instruction called at pc=%#x.", xc->readPC());
}}, IsNonSpeculative);
-
+ 0x55: m5anBegin({{
+ AlphaPseudo::anBegin(xc->tcBase(), R16);
+ }}, IsNonSpeculative);
+ 0x56: m5anWait({{
+ AlphaPseudo::anWait(xc->tcBase(), R16, R17);
+ }}, IsNonSpeculative);
}
}
#endif
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include "base/annotate.hh"
+#include "base/callback.hh"
+#include "base/output.hh"
+#include "base/trace.hh"
+#include "sim/root.hh"
+#include "sim/sim_exit.hh"
+#include "sim/system.hh"
+
+
+
+class AnnotateDumpCallback : public Callback
+{
+ public:
+ virtual void process();
+};
+
+void
+AnnotateDumpCallback::process()
+{
+ Annotate::annotations.dump();
+}
+
+namespace Annotate {
+
+
+Annotate annotations;
+
+Annotate::Annotate()
+{
+ registerExitCallback(new AnnotateDumpCallback);
+}
+
+void
+Annotate::add(System *sys, Addr stack, uint32_t sm, uint32_t st,
+ uint32_t wm, uint32_t ws)
+{
+ AnnotateData *an;
+
+ an = new AnnotateData;
+ an->time = curTick;
+
+ std::map<System*, std::string>::iterator i = nameCache.find(sys);
+ if (i == nameCache.end()) {
+ nameCache[sys] = sys->name();
+ }
+
+ an->system = nameCache[sys];
+ an->stack = stack;
+ an->stateMachine = sm;
+ an->curState = st;
+ an->waitMachine = wm;
+ an->waitState = ws;
+
+ data.push_back(an);
+ if (an->waitMachine)
+ DPRINTF(Annotate, "Annotating: %s(%#llX) %d:%d waiting on %d:%d\n",
+ an->system, an->stack, an->stateMachine, an->curState,
+ an->waitMachine, an->waitState);
+ else
+ DPRINTF(Annotate, "Annotating: %s(%#llX) %d:%d beginning\n", an->system,
+ an->stack, an->stateMachine, an->curState);
+
+ DPRINTF(Annotate, "Now %d events on list\n", data.size());
+
+}
+
+void
+Annotate::dump()
+{
+
+ std::list<AnnotateData*>::iterator i;
+
+ i = data.begin();
+
+ if (i == data.end())
+ return;
+
+ std::ostream *os = simout.create("annotate.dat");
+
+ AnnotateData *an;
+
+ while (i != data.end()) {
+ DPRINTF(Annotate, "Writing\n", data.size());
+ an = *i;
+ ccprintf(*os, "%d %s(%#llX) %d %d %d %d\n", an->time, an->system,
+ an->stack, an->stateMachine, an->curState, an->waitMachine,
+ an->waitState);
+ i++;
+ }
+}
+
+} //namespace Annotate
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __BASE__ANNOTATE_HH__
+#define __BASE__ANNOTATE_HH__
+
+#include "sim/host.hh"
+
+#include <string>
+#include <list>
+#include <map>
+
+
+class System;
+
+namespace Annotate {
+
+
+class Annotate {
+
+ protected:
+ struct AnnotateData {
+ Tick time;
+ std::string system;
+ Addr stack;
+ uint32_t stateMachine;
+ uint32_t curState;
+ uint32_t waitMachine;
+ uint32_t waitState;
+ };
+
+ std::list<AnnotateData*> data;
+ std::map<System*, std::string> nameCache;
+
+ public:
+ Annotate();
+ void add(System *sys, Addr stack, uint32_t sm, uint32_t st, uint32_t
+ wm, uint32_t ws);
+ void dump();
+};
+
+extern Annotate annotations;
+} //namespace Annotate
+
+#endif //__BASE__ANNOTATE_HH__
+
baseFlags = [
'Activity',
'AlphaConsole',
+ 'Annotate',
'BADADDR',
'BE',
'BPredRAS',
#include "sim/pseudo_inst.hh"
#include "arch/vtophys.hh"
+#include "base/annotate.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "cpu/quiesce_event.hh"
tc->getSystemPtr()->kernelSymtab->insert(addr,symbol);
}
+ void
+ anBegin(ThreadContext *tc, uint64_t cur)
+ {
+ Annotate::annotations.add(tc->getSystemPtr(), 0, cur >> 32, cur &
+ 0xFFFFFFFF, 0,0);
+ }
+
+ void
+ anWait(ThreadContext *tc, uint64_t cur, uint64_t wait)
+ {
+ Annotate::annotations.add(tc->getSystemPtr(), 0, cur >> 32, cur &
+ 0xFFFFFFFF, wait >> 32, wait & 0xFFFFFFFF);
+ }
+
+
void
dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
{
void debugbreak(ThreadContext *tc);
void switchcpu(ThreadContext *tc);
void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr);
+ void anBegin(ThreadContext *tc, uint64_t cur);
+ void anWait(ThreadContext *tc, uint64_t cur, uint64_t wait);
}
#define switchcpu_func 0x52
#define addsymbol_func 0x53
#define panic_func 0x54
+#define anbegin_func 0x55
+#define anwait_func 0x56
#define INST(op, ra, rb, func) \
.long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func))
#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func)
#define PANIC INST(m5_op, 0, 0, panic_func)
+#define AN_BEGIN(r1) INST(m5_op, r1, 0, anbegin_func)
+#define AN_WAIT(r1,r2) INST(m5_op, r1, r2, anwait_func)
.set noreorder
END(m5_panic)
+ .align 4
+LEAF(m5_anbegin)
+ AN_BEGIN(16)
+ RET
+END(m5_anbegin)
+
+
+ .align 4
+LEAF(m5_anwait)
+ AN_WAIT(16,17)
+ RET
+END(m5_anwait)
+
+
void m5_switchcpu(void);
void m5_addsymbol(uint64_t addr, char *symbol);
void m5_panic(void);
+void m5_anbegin(uint64_t s);
+void m5_anwait(uint64_t s, uint64_t w);
#endif // __M5OP_H__
projects / gem5.git / commitdiff