abc9_ops: -reintegrate to not trim box padding anymore

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index f9890a59210ae495d56801d6babc12a8e578310c..4f466d568116b31bb871415d6f8baa479e5dddeb 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -349,7 +349,7 @@ struct XAigerWriter
                                                unused_bits.erase(I);
                                        }
                                if (w->port_output)
-                                       for (const auto &b : rhs.bits()) {
+                                       for (const auto &b : rhs) {
                                                SigBit O = sigmap(b);
                                                if (O != b)
                                                        alias_map[O] = b;

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 463941b0b1b2dc9e54aa98c2bc07fbf91455ae00..aa21ff283f27d7f7835dfacad25985541aaeb2bd 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -562,15 +562,6 @@ void reintegrate(RTLIL::Module *module)
                                                c.wire = module->wires_.at(remap_name(c.wire->name));
                                        newsig.append(c);
                                }
-
-                               auto it = existing_cell->connections_.find(port_name);
-                               if (it == existing_cell->connections_.end())
-                                       continue;
-                               if (GetSize(newsig) > GetSize(it->second))
-                                       newsig = newsig.extract(0, GetSize(it->second));
-                               else
-                                       log_assert(GetSize(newsig) == GetSize(it->second));
-
                                cell->setPort(port_name, newsig);
 
                                if (w->port_input && !abc9_flop)