[sim, xcc] bthread threading model exposed; insn encoding cleaned up

diff --git a/riscv/execute.h b/riscv/execute.h
index abfa68e7aeb5a7d062158b6b74a13dad6b39442a..15f90efcd67800172974b9c9d62e1c7c11fe845d 100644 (file)
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -377,7 +377,7 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007fff) == 0xd4000000)
+        if((insn.bits & 0xfe0fffe0) == 0xd4000000)
         {
           #include "insns/mff_s.h"
           break;
@@ -386,7 +386,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x1:
       {
-        if((insn.bits & 0xfe007fff) == 0xd4001000)
+        if((insn.bits & 0xfe0fffe0) == 0xd4001000)
         {
           #include "insns/mff_d.h"
           break;
@@ -395,7 +395,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x4:
       {
-        if((insn.bits & 0xfe007fff) == 0xd4004000)
+        if((insn.bits & 0xfe0fffe0) == 0xd4004000)
         {
           #include "insns/mtf_s.h"
           break;
@@ -404,7 +404,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x5:
       {
-        if((insn.bits & 0xfe007fff) == 0xd4005000)
+        if((insn.bits & 0xfe0fffe0) == 0xd4005000)
         {
           #include "insns/mtf_d.h"
           break;
@@ -979,18 +979,18 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x2:
       {
-        if((insn.bits & 0xfe0fffe0) == 0xf6002000)
+        if((insn.bits & 0xfff07fe0) == 0xf6002000)
         {
-          #include "insns/rdhwr.h"
+          #include "insns/mfcr.h"
           break;
         }
         #include "insns/unimp.h"
       }
       case 0x3:
       {
-        if((insn.bits & 0xffffffff) == 0xf6003000)
+        if((insn.bits & 0xfe007fff) == 0xf6003000)
         {
-          #include "insns/sync.h"
+          #include "insns/mtcr.h"
           break;
         }
         #include "insns/unimp.h"
@@ -999,7 +999,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       {
         if((insn.bits & 0xffffffff) == 0xf6004000)
         {
-          #include "insns/syscall.h"
+          #include "insns/sync.h"
           break;
         }
         #include "insns/unimp.h"
@@ -1007,6 +1007,15 @@ switch((insn.bits >> 0x19) & 0x7f)
       case 0x5:
       {
         if((insn.bits & 0xffffffff) == 0xf6005000)
+        {
+          #include "insns/syscall.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xffffffff) == 0xf6006000)
         {
           #include "insns/break.h"
           break;
@@ -1026,7 +1035,7 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe0fffff) == 0xfc000000)
+        if((insn.bits & 0xffffffe0) == 0xfc000000)
         {
           #include "insns/ei.h"
           break;
@@ -1035,7 +1044,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x1:
       {
-        if((insn.bits & 0xfe0fffff) == 0xfc001000)
+        if((insn.bits & 0xffffffe0) == 0xfc001000)
         {
           #include "insns/di.h"
           break;
@@ -1053,7 +1062,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x4:
       {
-        if((insn.bits & 0xfe007fff) == 0xfc004000)
+        if((insn.bits & 0xfff07fe0) == 0xfc004000)
         {
           #include "insns/mfpcr.h"
           break;
@@ -1063,30 +1072,12 @@ switch((insn.bits >> 0x19) & 0x7f)
       case 0x5:
       {
         if((insn.bits & 0xfe007fff) == 0xfc005000)
-        {
-          #include "insns/mwfpcr.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x6:
-      {
-        if((insn.bits & 0xfe007fff) == 0xfc006000)
         {
           #include "insns/mtpcr.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x7:
-      {
-        if((insn.bits & 0xfe007fff) == 0xfc007000)
-        {
-          #include "insns/mwtpcr.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
       default:
       {
         #include "insns/unimp.h"

diff --git a/riscv/insns/di.h b/riscv/insns/di.h
index d3c70a9ac4522a5fbc6c3c910e0388f14ceb0f2b..f555c2c479260309cf016edc41186d02e4d13b51 100644 (file)
--- a/riscv/insns/di.h
+++ b/riscv/insns/di.h
@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr & ~SR_ET);
-RA = temp;
+RC = temp;

diff --git a/riscv/insns/ei.h b/riscv/insns/ei.h
index ca3586f7e0f35af3d03b2de5cc8a2fbbf571df2d..75d79fecd66bd208c3ca9af30771af0cd6347c4e 100644 (file)
--- a/riscv/insns/ei.h
+++ b/riscv/insns/ei.h
@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr | SR_ET);
-RA = temp;
+RC = temp;

diff --git a/riscv/insns/mfcr.h b/riscv/insns/mfcr.h
new file mode 100644 (file)
index 0000000..7ce1d9e
--- /dev/null
+++ b/riscv/insns/mfcr.h
@@ -0,0 +1,17 @@
+reg_t val;
+
+switch(insn.rtype.rb)
+{
+  case 1:
+    val = 32; // synci_step
+    break;
+
+  case 29:
+    val = tid;
+    break;
+
+  default:
+    val = -1;
+}
+
+RC = gprlen == 64 ? val : sext32(val);

diff --git a/riscv/insns/mff_d.h b/riscv/insns/mff_d.h
index eaece440b27eb579dd68dc00cf01a43ef0057fa6..e2e8415ce81e2a5a47cf5b4a214a88ec8d63466b 100644 (file)
--- a/riscv/insns/mff_d.h
+++ b/riscv/insns/mff_d.h
@@ -1,3 +1,3 @@
 require64;
 require_fp;
-RA = FRB;
+RC = FRA;

diff --git a/riscv/insns/mff_s.h b/riscv/insns/mff_s.h
index 6233a3f5944be54ebe76f0ec2bc32c30e0dc6eed..f92c935266ad9f55bb92b2003ea0800635242750 100644 (file)
--- a/riscv/insns/mff_s.h
+++ b/riscv/insns/mff_s.h
@@ -1,2 +1,2 @@
 require_fp;
-RA = sext32(FRB);
+RC = sext32(FRA);

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index 853842ecccd1a0c1e653270627ae8bbf11a39901..05ed297c5b0e380a743c429168c56351fb2912e2 100644 (file)
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -29,4 +29,4 @@ switch(insn.rtype.rb)
     val = -1;
 }
 
-RA = gprlen == 64 ? val : sext32(val);
+RC = gprlen == 64 ? val : sext32(val);

diff --git a/riscv/insns/mtcr.h b/riscv/insns/mtcr.h
new file mode 100644 (file)
index 0000000..5f85a51
--- /dev/null
+++ b/riscv/insns/mtcr.h
@@ -0,0 +1,8 @@
+reg_t val = gprlen == 64 ? RA : sext32(RA);
+
+switch(insn.rtype.rb)
+{
+  case 29:
+    tid = val;
+    break;
+}

diff --git a/riscv/insns/mtf_d.h b/riscv/insns/mtf_d.h
index fcee6a1ae9d0ac2ff6dce7e71b324823873f4703..4d3983335fe49dd835fef9e97a797a4cb52ddc09 100644 (file)
--- a/riscv/insns/mtf_d.h
+++ b/riscv/insns/mtf_d.h
@@ -1,3 +1,3 @@
 require64;
 require_fp;
-FRA = RB;
+FRC = RA;

diff --git a/riscv/insns/mtf_s.h b/riscv/insns/mtf_s.h
index a3b77376472965b2e632c21f4673d3c6db7e3740..239df16c7544458fab852db5d19c53d6ac38d7d4 100644 (file)
--- a/riscv/insns/mtf_s.h
+++ b/riscv/insns/mtf_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRA = sext32(RB);
+FRC = sext32(RA);

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 4fbef44a9bb0ce27d82ee59a57d0609c02ef5373..87bce5e4510d00c159d6e60575852e2a1a02aeb9 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -18,6 +18,7 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   ebase = 0;
   epc = 0;
   badvaddr = 0;
+  tid = 0;
   set_sr(SR_S | (support_64bit ? SR_KX : 0));
   set_fsr(0);
 

diff --git a/riscv/processor.h b/riscv/processor.h
index f2024ff6d799b88ada3dea5daa51dd20b9f7be10..942c491836255235261a03ddb7a8607f8e37e19b 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -21,13 +21,20 @@ private:
   // architected state
   reg_t R[NGPR];
   freg_t FR[NFPR];
+
+  // privileged control registers
   reg_t pc;
   reg_t epc;
   reg_t badvaddr;
   reg_t ebase;
   uint32_t id;
   uint32_t sr;
+
+  // unprivileged control registers
+  uint32_t tid;
   uint32_t fsr;
+
+  // 32-bit or 64-bit mode (redundant with sr)
   int gprlen;
 
   // shared memory