CRB-Form
-* crternlogi BF,BFA,BFB,TLI,msk
+* crfternlogi BF,BFA,BFB,TLI,msk
Pseudo-code:
CR field BF
+# Condition Register Field Ternary Bitwise Logic Immediate
+
+CRB-Form
+
+* crternlogi BT,BA,BB,TLI
+
+Pseudo-code:
+
+ idx <- CR[BT+32] || CR[BA+32] || CR[BB+32]
+ CR[4*BF+32] <- TLI[7-idx]
+
+Special Registers Altered:
+
+ CR field BF
+
# Condition Register Field Dynamic Binary Logic
CRB-Form
-* crbinlog BF,BFA,BFB,msk
+* crfbinlog BF,BFA,BFB,msk
Pseudo-code:
CR field BF
+# Condition Register Dynamic Binary Logic
+
+X-Form
+
+* crbinlog BT,BA,BFB
+
+Pseudo-code:
+
+ a <- CR[BT+32]
+ b <- CR[BA]
+ lut <- CR[4*BFB+32:4*BFB+35]
+ idx <- CR[BT+32] || CR[BA+32]
+ CR[BT+32] <- lut[3-idx]
+
+Special registers altered:
+
+ CR[BT+32]
+
# Add With Shift By Immediate
Z23-Form
creqv,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
crorc,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
cror,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0
-crbinlog,CROP,,1P,EXTRA3,NO,d:BF,s:BFA,s:BFB,0,0,0,0,0,BFA_BFB_BF,BF,0
-crternlogi,CROP,,1P,EXTRA3,NO,d:BF,s:BFA,s:BFB,0,0,0,0,0,BFA_BFB_BF,BF,0
+crfbinlog,CROP,,1P,EXTRA3,NO,d:BF,s:BFA,s:BFB,0,0,0,0,0,BFA_BFB_BF,BF,0
+crbinlog,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BFB,0,0,0,0,0,BA_BFB,BT,0
+crfternlogi,CROP,,1P,EXTRA3,NO,d:BF,s:BFA,s:BFB,0,0,0,0,0,BFA_BFB_BF,BF,0
cmp,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0
cmpl,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0
cmprb,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0
| PO | FRS | RA | RB | XO | / |
| PO | FRSp | RA | RB | XO | / |
| PO | BT | /// | /// | XO |Rc |
+ | PO | BT | BA | BFB // | XO | 1 |
| PO | /// | RA | RB | XO | / |
| PO | /// | /// | RB | XO | / |
| PO | /// | /// | /// | XO | / |
BA (11:15)
Field used to specify a bit in the CR to be used as
a source.
- Formats: XL
+ Formats: XL, X
BB (16:20)
Field used to specify a bit in the CR to be used as
a source.
BFB (16:18)
Field used to specify one of the CR fields
to be used as a source.
- Formats: CRB
+ Formats: CRB, X
BH (19:20)
Field used to specify a hint in the Branch Condi-
tional to Link Register and Branch Conditional to
BT (6:10)
Field used to specify a bit in the CR or in the
FPSCR to be used as a target.
- Formats: XL
+ Formats: XL, X
BX,B (30,16:20)
Fields that are concatenated to specify a VSR to
be used as a source.
-----01011-,ALU,OP_FISHMV,FRS,CONST_UI,NONE,FRS,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fishmv,DX,,1,unofficial until submitted and approved/renumbered by the opf isa wg
0101110110-,ALU,OP_BMAT,RA,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,gbbd,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
------00001,SHIFT_ROT,OP_BINLOG,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,binlog,BM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
------001001,CR,OP_CRBINLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crbinlog,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----001001,CR,OP_CRFBINLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crfbinlog,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+00001011101,CR,OP_CRBINLOG,NONE,NONE,NONE,NONE,BA_BFB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crbinlog,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2
--------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
---------01-,CR,OP_CRTERNLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crternlogi,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+--------010,CR,OP_CRFTERNLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crfternlogi,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg
------00100,ALU,OP_MADDSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddsubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
------01100,ALU,OP_MADDRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
------10100,ALU,OP_MSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,msubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
"brh", "brw", "brd",
'setvl', 'svindex', 'svremap', 'svstep',
'svshape', 'svshape2',
- 'binlog', 'crbinlog', 'crternlogi', 'ternlogi',
+ 'binlog', 'crbinlog', 'crfbinlog',
+ 'crternlogi', 'crfternlogi', 'ternlogi',
'bmask', 'cprop', 'gbbd',
'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd',
'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du",
comb += self.cr_bitfield_b.ok.eq(1)
comb += self.cr_bitfield_o.data.eq(self.dec.FormCRB.BF)
comb += self.cr_bitfield_o.ok.eq(1)
+ with m.Case(CRInSel.BA_BFB):
+ comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
+ comb += self.cr_bitfield.ok.eq(1)
+ comb += self.cr_bitfield_b.data.eq(self.dec.FormCRB.BFB)
+ comb += self.cr_bitfield_b.ok.eq(1)
+ comb += self.cr_bitfield_o.data.eq(self.dec.FormCRB.BF)
+ comb += self.cr_bitfield_o.ok.eq(1)
with m.Case(CRInSel.BC):
comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
comb += self.cr_bitfield.ok.eq(1)
"cprop", # AV bitmanip
"crand", "crandc", "creqv",
"crnand", "crnor", "cror", "crorc", "crxor",
- "crbinlog", # binary bitmanip
- "crternlogi", # ternary bitmanip
+ "crbinlog", "crfbinlog", # binary bitmanip (field and CR bit)
+ "crternlogi", "crfternlogi", # ternary bitmanip (field and CR bit)
"darn",
"dcbf", "dcbst", "dcbt", "dcbtst", "dcbz",
"divd", "divde", "divdeo", "divdeu",
OP_CRTERNLOG = 113
OP_BINLOG = 114
OP_CRBINLOG = 115
+ OP_CRFBINLOG = 116
+ OP_CRFTERNLOG = 117
class SelType(Enum):
CR1 = 7
BA = 8
BFA_BFB_BF = 9
+ BA_BFB = 10 # maaamma miiia... definitely time for CRin1/2 in CSV...
def __str__(self):
return self.name
# BF is marked as a dest but is actually also src
index1 = svp64_src.get('BFA', None)
index2 = svp64_src.get('BFB', None)
- index3 = svp64_dest.get('BF', None) # read-modify-write
- entry['sv_cr_in'] = "Idx_%d_%d_%d" % (index1, index2, index3)
+ # long story, a kludge should allow the 3rd source to be id'd
+ #index3 = svp64_dest.get('BF', None) # read-modify-write
+ entry['sv_cr_in'] = "Idx_%d_%d" % (index1, index2)
+ elif cr_in == 'BA_BFB':
+ # three indices, BT and BA are 5-bit source, BFB is 3-bit
+ # BF is marked as a dest but is actually also src
+ index1 = svp64_src.get('BA', None)
+ index2 = svp64_src.get('BFB', None)
+ entry['sv_cr_in'] = "Idx_%d_%d" % (index1, index2)
# CRout a lot easier. ignore WHOLE_REG for now
cr_out = entry['CR out']
# identify if it is a word instruction
record = DB[opcode]
+ #log("record", record)
if record is not None:
insn = WordInstruction.assemble(record=record, arguments=fields)
yield from insn.disassemble(record=record, style=Style.LEGACY)
v30b_op = opmodes.pop(0) # first is the v3.0B
record = DB[v30b_op]
+ #log("record v30b", record)
if record is not None:
insn = SVP64Instruction.assemble(record=record,
arguments=fields, specifiers=opmodes)
]
lst = [
#"sv.cmp/ff=gt *0,*1,*2,0",
- "dsld 5,4,5,3",
-
+ #"dsld 5,4,5,3",
+ "crfbinlog 3,4,5,15",
+ #"crbinlog 3,4,5",
]
isa = SVP64Asm(lst, macros=macros)
log("list:\n", "\n\t".join(list(isa)))
elif value == 'RM-1P-2S1D':
res['Etype'] = 'EXTRA3' # RM EXTRA3 type
- if insn_name in ['crbinlog', 'crternlogi']:
+ if insn_name in ['crfbinlog', 'crfternlogi']:
res['0'] = 'd:BF' # BF: Rdest1_EXTRA3
res['1'] = 's:BFA' # BFA: Rsrc1_EXTRA3
res['2'] = 's:BFB' # BFB: Rsrc2_EXTRA3
+ elif insn_name == 'crbinlog':
+ res['0'] = 'd:BT' # BT: Rdest1_EXTRA3
+ res['1'] = 's:BA' # BA: Rsrc1_EXTRA3
+ res['2'] = 's:BFB' # BFB: Rsrc2_EXTRA3
elif insn_name.startswith('cr'):
res['0'] = 'd:BT' # BT: Rdest1_EXTRA3
res['1'] = 's:BA' # BA: Rsrc1_EXTRA3
return result
+def crfbinlog(bf, bfa, bfb, mask):
+ lut = bfb
+ expected = bf&~mask # start at BF, mask overwrites masked bits only
+ checks = (bfa, bf) # LUT positions 1<<0=bfa 1<<1=bf
+ for i in range(4):
+ lut_index = 0
+ for j, check in enumerate(checks):
+ if check & (1<<i):
+ lut_index |= 1<<j
+ maskbit = (mask >> i) & 0b1
+ if (lut & (1<<lut_index)) and maskbit:
+ expected |= 1<<i
+ return expected
+
+
+def ternlogi(rc, rt, ra, rb, imm):
+ expected = 0
+ for i in range(64):
+ lut_index = 0
+ if rb & 2 ** i:
+ lut_index |= 2 ** 0
+ if ra & 2 ** i:
+ lut_index |= 2 ** 1
+ if rt & 2 ** i:
+ lut_index |= 2 ** 2
+ if imm & 2 ** lut_index:
+ expected |= 2 ** i
+ return expected
+
+
class BitManipTestCase(TestAccumulatorBase):
def case_gbbd(self):
lst = ["gbbd 0, 1"]
self.add_case(Program(lst, bigendian), initial_regs, expected=e)
- def do_case_crternlogi(self, bf, bfa, bfb, imm, mask):
- lst = [f"crternlogi 3,4,5,%d,%d" % (imm, mask)]
+ def do_case_crfternlogi(self, bf, bfa, bfb, imm, mask):
+ lst = [f"crfternlogi 3,4,5,%d,%d" % (imm, mask)]
# set up CR
bf %= 2 ** 4
bfa %= 2 ** 4
self.add_case(Program(lst, bigendian), initial_regs=None, expected=e,
initial_cr=initial_cr)
- def case_crternlogi_0(self):
- self.do_case_crternlogi(0b1111,
+ def case_crfternlogi_0(self):
+ self.do_case_crfternlogi(0b1111,
0b1100,
0b1010,
0x80, 0b1111)
- def case_crternlogi_random(self):
+ def case_crfternlogi_random(self):
for i in range(100):
- rc = bool(hash_256(f"crternlogi rc {i}") & 1)
- imm = hash_256(f"crternlogi imm {i}") & 0xFF
- bf = hash_256(f"crternlogi bf {i}") % 2 ** 4
- bfa = hash_256(f"crternlogi bfa {i}") % 2 ** 4
- bfb = hash_256(f"crternlogi bfb {i}") % 2 ** 4
- msk = hash_256(f"crternlogi msk {i}") % 2 ** 4
- self.do_case_crternlogi(bf, bfa, bfb, imm, msk)
+ rc = bool(hash_256(f"crfternlogi rc {i}") & 1)
+ imm = hash_256(f"crfternlogi imm {i}") & 0xFF
+ bf = hash_256(f"crfternlogi bf {i}") % 2 ** 4
+ bfa = hash_256(f"crfternlogi bfa {i}") % 2 ** 4
+ bfb = hash_256(f"crfternlogi bfb {i}") % 2 ** 4
+ msk = hash_256(f"crfternlogi msk {i}") % 2 ** 4
+ self.do_case_crfternlogi(bf, bfa, bfb, imm, msk)
- def do_case_crbinlog(self, bf, bfa, bfb, mask):
- lst = ["crbinlog 3,4,5,%d" % mask]
+ def do_case_crfbinlog(self, bf, bfa, bfb, mask):
+ lst = ["crfbinlog 3,4,5,%d" % mask]
# set up CR
bf %= 2 ** 4
bfa %= 2 ** 4
lst = list(SVP64Asm(lst, bigendian))
e = ExpectedState(pc=4)
- expected = bf&~mask # start at BF, mask overwrites masked bits only
- checks = (bfa, bf) # LUT positions 1<<0=bfa 1<<1=bf
- for i in range(4):
- lut_index = 0
- for j, check in enumerate(checks):
- if check & (1<<i):
- lut_index |= 1<<j
- maskbit = (mask >> i) & 0b1
- if (lut & (1<<lut_index)) and maskbit:
- expected |= 1<<i
- e.crregs[3] = expected
+ e.crregs[3] = crfbinlog(bf, bfa, bfb, mask)
e.crregs[4] = bfa
e.crregs[5] = bfb
self.add_case(Program(lst, bigendian), initial_regs=None, expected=e,
initial_cr=initial_cr)
- def case_crbinlog_0(self):
- self.do_case_crbinlog(0b1111,
- 0b1100,
- 0x8, 0b1111)
+ def case_crfbinlog_0(self):
+ self.do_case_crfbinlog(0b1111,
+ 0b1100,
+ 0x8, 0b1111)
- def case_crbinlog_random(self):
+ def case_crfbinlog_random(self):
for i in range(100):
- bf = hash_256(f"crbinlog bf {i}") % 2 ** 4
- bfa = hash_256(f"crbinlog bfa {i}") % 2 ** 4
- bfb = hash_256(f"crbinlog bfb {i}") % 2 ** 4
- msk = hash_256(f"crbinlog msk {i}") % 2 ** 4
- self.do_case_crbinlog(bf, bfa, bfb, msk)
+ bf = hash_256(f"crfbinlog bf {i}") % 2 ** 4
+ bfa = hash_256(f"crfbinlog bfa {i}") % 2 ** 4
+ bfb = hash_256(f"crfbinlog bfb {i}") % 2 ** 4
+ msk = hash_256(f"crfbinlog msk {i}") % 2 ** 4
+ self.do_case_crfbinlog(bf, bfa, bfb, msk)
def do_case_ternlogi(self, rc, rt, ra, rb, imm):
rc_dot = "." if rc else ""
projects / openpower-isa.git / commitdiff