Update 40.perlbmk simple-timing for 8k blk_size

--HG--
extra : convert_revision : 461751061dc5db076f11e9c3b37da25cc47c583e

diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini
index fa4ee72daf398892a9ec54cafffd8af606c3fdcd..5f64dcebdcba62c7e67c9ccc517ad0484268521f 100644 (file)
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini
@@ -7,21 +7,6 @@ max_tick=0
 output_file=cout
 progress_interval=0
 
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
 [serialize]
 count=10
 cycle=0
@@ -197,11 +182,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing
+cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
 egid=100
 env=
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 output=cout
@@ -223,14 +208,6 @@ type=PhysicalMemory
 file=
 latency=1
 range=0:134217727
+zero=false
 port=system.membus.port[0]
 
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-

diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out
index ea12fcb9ae257445a0dbe4c67b32118033a053ef..6998f482835b4c1ad3c47c64c5683d9f6280b8a8 100644 (file)
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out
@@ -10,6 +10,7 @@ type=PhysicalMemory
 file=
 range=[0,134217727]
 latency=1
+zero=false
 
 [system]
 type=System
@@ -26,11 +27,11 @@ responder_set=false
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
 input=cin
 output=cout
 env=
-cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing
+cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
 system=system
 uid=100
 euid=100
@@ -178,15 +179,6 @@ prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
 hit_latency=1
 
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
 [stats]
 descriptions=true
 project_name=test
@@ -204,25 +196,6 @@ dump_cycle=0
 dump_period=0
 ignore_events=
 
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
 [statsreset]
 reset_cycle=0
 

diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt
index 4d20e663a491f9e3ecaab93492eb352d1c260a9d..45f793ab7565d4a2376a3eace18bb0fd41e05c3e 100644 (file)
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,67 +1,67 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 502967                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 217744                       # Number of bytes of host memory used
-host_seconds                                  3994.27                       # Real time elapsed on the host
-host_tick_rate                                1895851                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 752631                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 230876                       # Number of bytes of host memory used
+host_seconds                                  2669.29                       # Real time elapsed on the host
+host_tick_rate                                2836913                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  2008987724                       # Number of instructions simulated
+sim_insts                                  2008987607                       # Number of instructions simulated
 sim_seconds                                  0.007573                       # Number of seconds simulated
-sim_ticks                                  7572549003                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses          511070058                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  3107.171711                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2107.171711                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              509611866                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     4530852932                       # number of ReadReq miss cycles
+sim_ticks                                  7572532003                       # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses          511070026                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  3107.171986                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2107.171986                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              509611834                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency     4530853333                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.002853                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses              1458192                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   3072660932                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   3072661333                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.002853                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses         1458192                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses         210794909                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency  3884.294897                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2884.294897                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             210722955                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     279490555                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_accesses         210794896                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency  3884.267929                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2884.267929                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             210722944                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency     279480846                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.000341                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses               71954                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency    207536555                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_misses               71952                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency    207528846                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000341                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          71954                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 470.762150                       # Average number of references to valid blocks.
+system.cpu.dcache.WriteReq_mshr_misses          71952                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets     no value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                 470.762737                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           721864967                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  3143.715362                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  2143.715362                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               720334821                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency      4810343487                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_accesses           721864922                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  3143.713388                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  2143.713388                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               720334778                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency      4810334179                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.002120                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1530146                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses               1530144                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   3280197487                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   3280190179                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.002120                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1530146                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses          1530144                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses          721864967                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  3143.715362                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  2143.715362                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              720334821                       # number of overall hits
-system.cpu.dcache.overall_miss_latency     4810343487                       # number of overall miss cycles
+system.cpu.dcache.overall_accesses          721864922                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  3143.713388                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  2143.713388                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits              720334778                       # number of overall hits
+system.cpu.dcache.overall_miss_latency     4810334179                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.002120                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1530146                       # number of overall misses
+system.cpu.dcache.overall_misses              1530144                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   3280197487                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   3280190179                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.002120                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1530146                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses         1530144                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -73,57 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued            0
 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements                1526050                       # number of replacements
-system.cpu.dcache.sampled_refs                1530146                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                1526048                       # number of replacements
+system.cpu.dcache.sampled_refs                1530144                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4087.472566                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                720334821                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               35194000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                    74591                       # number of writebacks
-system.cpu.icache.ReadReq_accesses         2008987725                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  3103.752500                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  2103.752500                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits             2008977127                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       32893569                       # number of ReadReq miss cycles
+system.cpu.dcache.tagsinuse               4087.479154                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                720334778                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               35165000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                    74589                       # number of writebacks
+system.cpu.icache.ReadReq_accesses         2008987608                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  3103.627312                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  2103.627312                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits             2008977012                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       32886035                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000005                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                10598                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     22295569                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses                10596                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency     22290035                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000005                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           10598                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               189561.910455                       # Average number of references to valid blocks.
+system.cpu.icache.ReadReq_mshr_misses           10596                       # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets     no value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_refs               189597.679502                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses          2008987725                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  3103.752500                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  2103.752500                       # average overall mshr miss latency
-system.cpu.icache.demand_hits              2008977127                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        32893569                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses          2008987608                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  3103.627312                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  2103.627312                       # average overall mshr miss latency
+system.cpu.icache.demand_hits              2008977012                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        32886035                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000005                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 10598                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses                 10596                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     22295569                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     22290035                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000005                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            10598                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses            10596                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses         2008987725                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  3103.752500                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  2103.752500                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits             2008977127                       # number of overall hits
-system.cpu.icache.overall_miss_latency       32893569                       # number of overall miss cycles
+system.cpu.icache.overall_accesses         2008987608                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  3103.627312                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  2103.627312                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits             2008977012                       # number of overall hits
+system.cpu.icache.overall_miss_latency       32886035                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000005                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                10598                       # number of overall misses
+system.cpu.icache.overall_misses                10596                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     22295569                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     22290035                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000005                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           10598                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses           10596                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -135,64 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued            0
 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements                   9048                       # number of replacements
-system.cpu.icache.sampled_refs                  10598                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                   9046                       # number of replacements
+system.cpu.icache.sampled_refs                  10596                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1472.251444                       # Cycle average of tags in use
-system.cpu.icache.total_refs               2008977127                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1471.254279                       # Cycle average of tags in use
+system.cpu.icache.total_refs               2008977012                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses           1540744                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency  2153.831026                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1111.660796                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_accesses           1540740                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency  2153.828221                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1111.659139                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                 33878                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    3245534743                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency    3245521901                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.978012                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1506866                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1675123857                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_misses             1506862                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1675116913                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.978012                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1506866                       # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_accesses        74591                       # number of WriteReqNoAck|Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteReqNoAck|Writeback_hits        73517                       # number of WriteReqNoAck|Writeback hits
-system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate     0.014399                       # miss rate for WriteReqNoAck|Writeback accesses
-system.cpu.l2cache.WriteReqNoAck|Writeback_misses         1074                       # number of WriteReqNoAck|Writeback misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate     0.014399                       # mshr miss rate for WriteReqNoAck|Writeback accesses
-system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses         1074                       # number of WriteReqNoAck|Writeback MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.071270                       # Average number of references to valid blocks.
+system.cpu.l2cache.ReadReq_mshr_misses        1506862                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses           74589                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits               73515                       # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate       0.014399                       # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses              1074                       # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate     0.014399                       # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses         1074                       # number of Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets     no value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs                  0.071269                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            1540744                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency  2153.831026                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency  1111.660796                       # average overall mshr miss latency
+system.cpu.l2cache.demand_accesses            1540740                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency  2153.828221                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency  1111.659139                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                  33878                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     3245534743                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency     3245521901                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate          0.978012                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              1506866                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses              1506862                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   1675123857                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   1675116913                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_rate     0.978012                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         1506866                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses         1506862                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses           1615335                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency  2152.297003                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency  1111.660796                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                107395                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    3245534743                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.933515                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             1507940                       # number of overall misses
+system.cpu.l2cache.overall_accesses           1615329                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency  2152.294196                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency  1111.659139                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits                107393                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    3245521901                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.933516                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             1507936                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   1675123857                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.932850                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        1506866                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   1675116913                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.932851                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        1506862                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -204,17 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued            0
 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements               1474098                       # number of replacements
-system.cpu.l2cache.sampled_refs               1506866                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements               1474094                       # number of replacements
+system.cpu.l2cache.sampled_refs               1506862                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             32444.673070                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  107395                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle             164218000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   66806                       # number of writebacks
+system.cpu.l2cache.tagsinuse             32444.706916                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  107393                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle             164189000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                   66804                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       7572549003                       # number of cpu cycles simulated
-system.cpu.num_insts                       2008987724                       # Number of instructions executed
-system.cpu.num_refs                         722390480                       # Number of memory references
+system.cpu.numCycles                       7572532003                       # number of cpu cycles simulated
+system.cpu.num_insts                       2008987607                       # Number of instructions executed
+system.cpu.num_refs                         722390435                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------

diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr
index 9135960d0e1c2bd33e2494ae0f9bc7f3d0186ee6..bc72461c85399d9a1eec0121f328bc0b54bd7cb6 100644 (file)
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr
+++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr
@@ -1,2 +1,3 @@
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
 warn: Entering event queue @ 0.  Starting simulation...
 warn: ignoring syscall sigprocmask(1, 0, ...)