(no commit message)

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 674b406a6f722030c82f858a30854d4dc8cb078a..551d54a16d7ca0f9b52fe5df8ebb74c80c5e0a43 100644 (file)
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -7,6 +7,10 @@ A minimum of 3 register files are required for POWER:
 * Control and Condition Code Registers (CR0-7, CTR, LR)
 * SPRs (Special Purpose Registers)
 
+Source code:
+
+* <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;hb=HEAD>
+
 For a GPU, the FP and Integer registers need to be a massive 128 x 64-bit.
 
 # Regfile groups, Port Allocations and bit-widths