gallium: Add a cap to check if the driver supports ARB_post_depth_coverage
authorLyude <lyude@redhat.com>
Wed, 24 May 2017 19:42:39 +0000 (15:42 -0400)
committerIlia Mirkin <imirkin@alum.mit.edu>
Sat, 3 Jun 2017 03:19:22 +0000 (23:19 -0400)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
17 files changed:
src/gallium/docs/source/screen.rst
src/gallium/drivers/etnaviv/etnaviv_screen.c
src/gallium/drivers/freedreno/freedreno_screen.c
src/gallium/drivers/i915/i915_screen.c
src/gallium/drivers/llvmpipe/lp_screen.c
src/gallium/drivers/nouveau/nv30/nv30_screen.c
src/gallium/drivers/nouveau/nv50/nv50_screen.c
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
src/gallium/drivers/r300/r300_screen.c
src/gallium/drivers/r600/r600_pipe.c
src/gallium/drivers/radeonsi/si_pipe.c
src/gallium/drivers/softpipe/sp_screen.c
src/gallium/drivers/svga/svga_screen.c
src/gallium/drivers/swr/swr_screen.cpp
src/gallium/drivers/vc4/vc4_screen.c
src/gallium/drivers/virgl/virgl_screen.c
src/gallium/include/pipe/p_defines.h

index 871669c0d98f8ccbd6616c6066b5ee5db6520eae..852c31b24c397a61da6d8c44bc6d15524748b31a 100644 (file)
@@ -392,6 +392,8 @@ The integer capabilities:
 * ``PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX``: Whether a buffer with just
   PIPE_BIND_CONSTANT_BUFFER can be legally passed to set_vertex_buffers.
 * ``PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION``: As the name says.
+* ``PIPE_CAP_POST_DEPTH_COVERAGE``: whether
+  ``TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE`` is supported.
 
 
 .. _pipe_capf:
index bf13184ad61fdb6eab2aa1420a647a9f5a9e04b6..8fd118438bd14d877ad9ebd8764f3ae1e87c0300 100644 (file)
@@ -256,6 +256,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
+   case PIPE_CAP_POST_DEPTH_COVERAGE:
       return 0;
 
    /* Stream output. */
index b1501d5af0e6016e823124c653019f9b887738be..64811f835f59955933ad24c836bf4f91f3eb5e34 100644 (file)
@@ -314,6 +314,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
        case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
        case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
+       case PIPE_CAP_POST_DEPTH_COVERAGE:
                return 0;
 
        case PIPE_CAP_MAX_VIEWPORTS:
index 1cf9441ef11792fb8766f4af2f1bdc7fd4bdedbc..a0dbc124cbf4b0916edd513acffc3f63702ee201 100644 (file)
@@ -277,6 +277,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
+   case PIPE_CAP_POST_DEPTH_COVERAGE:
       return 0;
 
    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
index 656de49549700a0ee36a813e26c393848455e7f4..4e8c110d2679890083e66f47718e070e3cd9077e 100644 (file)
@@ -354,6 +354,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
+   case PIPE_CAP_POST_DEPTH_COVERAGE:
       return 0;
    }
    /* should only get here on unhandled cases */
index e8d14bfea41a425214471cee99751c6e8c801c8f..553ee496ea54fde90cda5dd72822b1b661da5081 100644 (file)
@@ -218,6 +218,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TGSI_BALLOT:
    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
+   case PIPE_CAP_POST_DEPTH_COVERAGE:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index 59afd14fac2f6618b65f572d79005697b461ccb5..631b2c9a829cd12189dd9489a8b090a97f3fb05d 100644 (file)
@@ -270,6 +270,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
    case PIPE_CAP_TGSI_BALLOT:
    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
+   case PIPE_CAP_POST_DEPTH_COVERAGE:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index f6c5c7279798141f858b828d8db5ace90435a7cd..cf376a631a1f6ce3ad9f98fc6182ca95a68df00b 100644 (file)
@@ -299,6 +299,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
    case PIPE_CAP_INT64_DIVMOD:
    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
+   case PIPE_CAP_POST_DEPTH_COVERAGE:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index 3452d92d9dd947426c67c06a38611d7932e27581..346ce0545c2b59456c571c8cdbef137a193d037f 100644 (file)
@@ -240,6 +240,7 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
         case PIPE_CAP_TGSI_BALLOT:
         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
+        case PIPE_CAP_POST_DEPTH_COVERAGE:
             return 0;
 
         /* SWTCL-only features. */
index 71dc16e50611c89b09a228aefe52aa75ac6ae9cb..957431a514131e1c964765907017049388c174ef 100644 (file)
@@ -395,6 +395,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
        case PIPE_CAP_TGSI_BALLOT:
        case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
+       case PIPE_CAP_POST_DEPTH_COVERAGE:
                return 0;
 
        case PIPE_CAP_DOUBLES:
index de4e5da0e03ebdba0ccab7b9d4a0d0166dced442..bbb5ea660d64ef2a1c08a9fe47e1df0f34e99096 100644 (file)
@@ -536,6 +536,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_TGSI_MUL_ZERO_WINS:
        case PIPE_CAP_UMA:
        case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
+       case PIPE_CAP_POST_DEPTH_COVERAGE:
                return 0;
 
        case PIPE_CAP_QUERY_BUFFER_OBJECT:
index 878953406853e843b15859bb2829232688fb26d1..de2649441c20c205a312d823d6a66764f2373a2a 100644 (file)
@@ -304,6 +304,7 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
+   case PIPE_CAP_POST_DEPTH_COVERAGE:
       return 0;
    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
       return 4;
index 74e5485c0ef6b0f1cf31e1d896e2cc970a123fc5..5ffb6c8f49985da607f107180ef07c3d8c31a587 100644 (file)
@@ -443,6 +443,7 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
+   case PIPE_CAP_POST_DEPTH_COVERAGE:
       return 0;
    }
 
index cdb8165d3db4a2bdac296c98c0ee6a077a9eb8c8..7931d19de2d3eb0ceb160979bdda3fda0819703c 100644 (file)
@@ -339,6 +339,7 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
+   case PIPE_CAP_POST_DEPTH_COVERAGE:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index 0d3eb3ce2371560b8dc9ff11beda29e6f09b7992..1f66d4cd1bfd1b7412652fc113476a83d81a124b 100644 (file)
@@ -255,6 +255,7 @@ vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
        case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
        case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
+        case PIPE_CAP_POST_DEPTH_COVERAGE:
                 return 0;
 
                 /* Stream output. */
index f1d41ba1d41f642a0fc870f35148ac9f2ad36789..456381e83200bf40a2e9305fa316fd7fd7eb3c12 100644 (file)
@@ -263,6 +263,7 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
+   case PIPE_CAP_POST_DEPTH_COVERAGE:
       return 0;
    case PIPE_CAP_VENDOR_ID:
       return 0x1af4;
index 769c94f32efc568c50fbf2e5884af0025cdb6dcb..c02bbdb7ee47580590b2888d044fb646f1bdaf36 100644 (file)
@@ -772,6 +772,7 @@ enum pipe_cap
    PIPE_CAP_TGSI_TES_LAYER_VIEWPORT,
    PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX,
    PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION,
+   PIPE_CAP_POST_DEPTH_COVERAGE,
 };
 
 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)