return cvt
-def FPMULADD32(FRA, FRB, FRC, addsign, mulsign):
+def FPMULADD32(FRA, FRC, FRB, addsign, mulsign):
from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
#return FPMUL64(FRA, FRB)
#FRA = DOUBLE(SINGLE(FRA))
#FRB = DOUBLE(SINGLE(FRB))
if addsign == 1:
- result = float(FRC)
+ result = float(FRB)
elif addsign == -1:
- result = -float(FRC)
+ result = -float(FRB)
elif addsign == 0:
result = 0.0
if mulsign == 1:
- result += float(FRA) * float(FRB)
+ result += float(FRA) * float(FRC)
elif mulsign == -1:
- result -= float(FRA) * float(FRB)
+ result -= float(FRA) * float(FRC)
log ("FPMULADD32", FRA, FRB, FRC,
float(FRA), float(FRB), float(FRC),
result)