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diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 31d100c96979a76a4610ee62d1595a7d8e59d1a0..51dafd6924a2cf363b30318ea1c4e6c0e4813780 100644 (file)
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -222,7 +222,8 @@ Vector Indexed Mode, when elwidth overrides are applied.
 The source override applies to RB, and before adding to
 RA in order to calculate the Effective Address, if SEA is
 set RB is sign-extended from elwidth bits to the full 64
-bits.
+bits.  For other Modes (ffirst, saturate),
+all EA computation is unsigned.
 
 Note that cache-inhibited LD/ST (`ldcix`) when VSPLAT is activated will perform **multiple** LD/ST operations, sequentially.  `ldcix` even with scalar src will read the same memory location *multiple times*, storing the result in successive Vector destination registers.  This because the cache-inhibit instructions are used to read and write memory-mapped peripherals.
 If a genuine cache-inhibited LD-VSPLAT is required then a *scalar*