mem: Fix MSHR assert triggering for invalidated prefetches

This changeset updates an assert in src/mem/cache/mshr.cc which was
erroneously catching invalidated prefetch requests. These requests can
become invalidated if another component writes (an exclusive access)
to this location during the time that the read request is in
flight. The original assert made the assumption that these cases can
only occur for reads generated by the CPU, and hence
prefetcher-generated requests would sometimes trip the assert.

Change-Id: If4f043273a688c2bab8f7a641192a2b583e7b20e
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index e3282f9b88948e4f316ce42af051cb0d8802a506..25f73d79a9c65b9fa1b87fb550dfff24c17a87c1 100644 (file)
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, 2015-2016 ARM Limited
+ * Copyright (c) 2012-2013, 2015-2017 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -465,7 +465,8 @@ MSHR::extractServiceableTargets(PacketPtr pkt)
     // avoid memory consistency violations.
     if (pkt->cmd == MemCmd::ReadRespWithInvalidate) {
         auto it = targets.begin();
-        assert(it->source == Target::FromCPU);
+        assert((it->source == Target::FromCPU) ||
+               (it->source == Target::FromPrefetcher));
         ready_targets.push_back(*it);
         it = targets.erase(it);
         while (it != targets.end()) {