2009-11-09 Tristan Gingold <gingold@adacore.com>

	* avr/interp.c (sim_resume): Fix typo for OP_ret.

diff --git a/sim/ChangeLog b/sim/ChangeLog
index 72736f497a41e2fb924d6e18d550512cba41da92..6a5e74e5bb219b418bef22eda6ffdecde0f70f65 100644 (file)
--- a/sim/ChangeLog
+++ b/sim/ChangeLog
@@ -1,3 +1,7 @@
+2009-11-09  Tristan Gingold  <gingold@adacore.com>
+
+       * avr/interp.c (sim_resume): Fix typo for OP_ret.
+
 2009-10-23  Doug Evans  <dje@sebabeach.org>
 
        * cris/arch.c: Regenerate.

diff --git a/sim/avr/interp.c b/sim/avr/interp.c
index 8bb9ec2e6a3b3bf4b141472c3a12ec8a5dde4baa..903370f8c28532b7e7a1aaad4b14e95da726c1a4 100644 (file)
--- a/sim/avr/interp.c
+++ b/sim/avr/interp.c
@@ -985,7 +985,7 @@ sim_resume (SIM_DESC sd, int step, int signal)
            unsigned int sp = read_word (REG_SP);
            if (avr_pc22)
              {
-               pc = sram[++sp] = pc << 16;
+               pc = sram[++sp] << 16;
                cycles++;
              }
            else