targets/kcu105: remove main_ram_size_limit

diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index be25e3c25ed41046c5aebcf511992545f32a7eed..a6241173b2aa4f988583acbc4c2f74994f45a4fb 100755 (executable)
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -96,8 +96,7 @@ class BaseSoC(SoCSDRAM):
             sdram_module = EDY4016A(sys_clk_freq, "1:4")
             self.register_sdram(self.ddrphy,
                 geom_settings       = sdram_module.geom_settings,
-                timing_settings     = sdram_module.timing_settings,
-                main_ram_size_limit = 0x40000000)
+                timing_settings     = sdram_module.timing_settings)
 
 # EthernetSoC --------------------------------------------------------------------------------------