indent text of lbzu description

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 20252b28088b80d39b6ae712ec8d031b149b96aa..3bedcb29ecc8d702bd6bfa186bd72b40327d4abc 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -78,13 +78,13 @@ Pseudo-code:
 
 Description:
 
-Let the effective address (EA) be the sum (RA)+ D. The
-byte in storage addressed by EA is loaded into RT[56:63].
-RT[0:55] are set to 0.
+    Let the effective address (EA) be the sum (RA)+ D. The
+    byte in storage addressed by EA is loaded into RT[56:63].
+    RT[0:55] are set to 0.
 
-EA is placed into register RA.
+    EA is placed into register RA.
 
-If RA=0 or RA=RT, the instruction form is invalid.
+    If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered: