}
fs_inst *
-brw_blorp_eu_emitter::emit_cmp(int op,
+brw_blorp_eu_emitter::emit_cmp(enum brw_conditional_mod op,
const struct brw_reg &x,
const struct brw_reg &y)
{
inline void emit_cond_mov(const struct brw_reg &x,
const struct brw_reg &y,
- int op,
+ enum brw_conditional_mod op,
const struct brw_reg &dst,
const struct brw_reg &src)
{
insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_RNDD, dst, src));
}
- inline void emit_cmp_if(int op,
+ inline void emit_cmp_if(enum brw_conditional_mod op,
const struct brw_reg &x,
const struct brw_reg &y)
{
}
private:
- fs_inst *emit_cmp(int op, const struct brw_reg &x, const struct brw_reg &y);
+ fs_inst *emit_cmp(enum brw_conditional_mod op, const struct brw_reg &x,
+ const struct brw_reg &y);
void *mem_ctx;
exec_list insts;
#define GEN6_COMPRESSION_1H 0
#define GEN6_COMPRESSION_2H 2
-#define BRW_CONDITIONAL_NONE 0
-#define BRW_CONDITIONAL_Z 1
-#define BRW_CONDITIONAL_NZ 2
-#define BRW_CONDITIONAL_EQ 1 /* Z */
-#define BRW_CONDITIONAL_NEQ 2 /* NZ */
-#define BRW_CONDITIONAL_G 3
-#define BRW_CONDITIONAL_GE 4
-#define BRW_CONDITIONAL_L 5
-#define BRW_CONDITIONAL_LE 6
-#define BRW_CONDITIONAL_R 7
-#define BRW_CONDITIONAL_O 8
-#define BRW_CONDITIONAL_U 9
+enum PACKED brw_conditional_mod {
+ BRW_CONDITIONAL_NONE = 0,
+ BRW_CONDITIONAL_Z = 1,
+ BRW_CONDITIONAL_NZ = 2,
+ BRW_CONDITIONAL_EQ = 1, /* Z */
+ BRW_CONDITIONAL_NEQ = 2, /* NZ */
+ BRW_CONDITIONAL_G = 3,
+ BRW_CONDITIONAL_GE = 4,
+ BRW_CONDITIONAL_L = 5,
+ BRW_CONDITIONAL_LE = 6,
+ BRW_CONDITIONAL_R = 7,
+ BRW_CONDITIONAL_O = 8,
+ BRW_CONDITIONAL_U = 9,
+};
#define BRW_DEBUG_NONE 0
#define BRW_DEBUG_BREAKPOINT 1
/* Returns the corresponding conditional mod for swapping src0 and
* src1 in e.g. CMP.
*/
-uint32_t
+enum brw_conditional_mod
brw_swap_cmod(uint32_t cmod)
{
switch (cmod) {
* channel.
*/
brw_inst *brw_IF(struct brw_compile *p, unsigned execute_size);
-brw_inst *gen6_IF(struct brw_compile *p, uint32_t conditional,
+brw_inst *gen6_IF(struct brw_compile *p, enum brw_conditional_mod conditional,
struct brw_reg src0, struct brw_reg src1);
void brw_ELSE(struct brw_compile *p);
void brw_set_uip_jip(struct brw_compile *p);
-uint32_t brw_swap_cmod(uint32_t cmod);
+enum brw_conditional_mod brw_swap_cmod(uint32_t cmod);
/* brw_eu_compact.c */
void brw_init_compaction_tables(struct brw_context *brw);
* embedded comparison (conditional modifier). It is not used on gen7.
*/
brw_inst *
-gen6_IF(struct brw_compile *p, uint32_t conditional,
+gen6_IF(struct brw_compile *p, enum brw_conditional_mod conditional,
struct brw_reg src0, struct brw_reg src1)
{
const struct brw_context *brw = p->brw;
/** Gen6 IF with embedded comparison. */
fs_inst *
-fs_visitor::IF(const fs_reg &src0, const fs_reg &src1, uint32_t condition)
+fs_visitor::IF(const fs_reg &src0, const fs_reg &src1,
+ enum brw_conditional_mod condition)
{
assert(brw->gen == 6);
fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF,
* the flag register with the packed 16 bits of the result.
*/
fs_inst *
-fs_visitor::CMP(fs_reg dst, fs_reg src0, fs_reg src1, uint32_t condition)
+fs_visitor::CMP(fs_reg dst, fs_reg src0, fs_reg src1,
+ enum brw_conditional_mod condition)
{
fs_inst *inst;
fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
fs_inst *IF(uint32_t predicate);
- fs_inst *IF(const fs_reg &src0, const fs_reg &src1, uint32_t condition);
+ fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
+ enum brw_conditional_mod condition);
fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
- uint32_t condition);
+ enum brw_conditional_mod condition);
fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
const fs_reg &x);
fs_inst *DEP_RESOLVE_MOV(int grf);
fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
const fs_reg &a);
- void emit_minmax(uint32_t conditionalmod, const fs_reg &dst,
+ void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
const fs_reg &src0, const fs_reg &src1);
bool try_emit_saturate(ir_expression *ir);
bool try_emit_mad(ir_expression *ir);
void emit_fp_minmax(const struct prog_instruction *fpi,
fs_reg dst, fs_reg src0, fs_reg src1);
- void emit_fp_sop(uint32_t conditional_mod,
+ void emit_fp_sop(enum brw_conditional_mod conditional_mod,
const struct prog_instruction *fpi,
fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
inst->src[i] = entry->src;
progress = true;
} else if (i == 0 && inst->src[1].file != IMM) {
- uint32_t new_cmod;
+ enum brw_conditional_mod new_cmod;
new_cmod = brw_swap_cmod(inst->conditional_mod);
if (new_cmod != ~0u) {
fs_visitor::emit_fp_minmax(const prog_instruction *fpi,
fs_reg dst, fs_reg src0, fs_reg src1)
{
- uint32_t conditionalmod;
+ enum brw_conditional_mod conditionalmod;
if (fpi->Opcode == OPCODE_MIN)
conditionalmod = BRW_CONDITIONAL_L;
else
}
void
-fs_visitor::emit_fp_sop(uint32_t conditional_mod,
+fs_visitor::emit_fp_sop(enum brw_conditional_mod conditional_mod,
const struct prog_instruction *fpi,
fs_reg dst, fs_reg src0, fs_reg src1,
fs_reg one)
}
void
-fs_visitor::emit_minmax(uint32_t conditionalmod, const fs_reg &dst,
+fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
const fs_reg &src0, const fs_reg &src1)
{
fs_inst *inst;
}
}
-static int
+static enum brw_conditional_mod
cond_for_alpha_func(GLenum func)
{
switch(func) {
return BRW_REGISTER_TYPE_F;
}
-uint32_t
+enum brw_conditional_mod
brw_conditional_for_comparison(unsigned int op)
{
switch (op) {
uint8_t mlen; /**< SEND message length */
int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
uint8_t target; /**< MRT target. */
- uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */
+ enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
bool force_writemask_all:1;
bool no_dd_clear:1;
#endif /* __cplusplus */
enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
-uint32_t brw_conditional_for_comparison(unsigned int op);
+enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
uint32_t brw_math_function(enum opcode op);
const char *brw_instruction_name(enum opcode op);
vec4_instruction *ASR(const dst_reg &dst, const src_reg &src0,
const src_reg &src1);
vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
- uint32_t condition);
- vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
+ enum brw_conditional_mod condition);
+ vec4_instruction *IF(src_reg src0, src_reg src1,
+ enum brw_conditional_mod condition);
vec4_instruction *IF(uint32_t predicate);
vec4_instruction *PULL_CONSTANT_LOAD(const dst_reg &dst,
const src_reg &index);
/** Walks an exec_list of ir_instruction and sends it through this visitor. */
void visit_instructions(const exec_list *list);
- void emit_vp_sop(uint32_t condmod, dst_reg dst,
+ void emit_vp_sop(enum brw_conditional_mod condmod, dst_reg dst,
src_reg src0, src_reg src1, src_reg one);
void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
void emit_if_gen6(ir_if *ir);
- void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1);
+ void emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
+ src_reg src0, src_reg src1);
void emit_lrp(const dst_reg &dst,
const src_reg &x, const src_reg &y, const src_reg &a);
inst->src[arg] = value;
return true;
} else if (arg == 0 && inst->src[1].file != IMM) {
- uint32_t new_cmod;
+ enum brw_conditional_mod new_cmod;
new_cmod = brw_swap_cmod(inst->conditional_mod);
if (new_cmod != ~0u) {
/** Gen6 IF with embedded comparison. */
vec4_instruction *
-vec4_visitor::IF(src_reg src0, src_reg src1, uint32_t condition)
+vec4_visitor::IF(src_reg src0, src_reg src1,
+ enum brw_conditional_mod condition)
{
assert(brw->gen == 6);
* the flag register with the packed 16 bits of the result.
*/
vec4_instruction *
-vec4_visitor::CMP(dst_reg dst, src_reg src0, src_reg src1, uint32_t condition)
+vec4_visitor::CMP(dst_reg dst, src_reg src0, src_reg src1,
+ enum brw_conditional_mod condition)
{
vec4_instruction *inst;
}
void
-vec4_visitor::emit_minmax(uint32_t conditionalmod, dst_reg dst,
+vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
src_reg src0, src_reg src1)
{
vec4_instruction *inst;
using namespace brw;
void
-vec4_visitor::emit_vp_sop(uint32_t conditional_mod,
+vec4_visitor::emit_vp_sop(enum brw_conditional_mod conditional_mod,
dst_reg dst, src_reg src0, src_reg src1,
src_reg one)
{
* and set various fields. This is the actual hardware format.
*/
+#include "main/compiler.h"
#include "brw_defines.h"
#include "gen8_instruction.h"