--- /dev/null
+# -*- coding: utf-8 -*-
+# Copyright (c) 2017 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+""" This file creates a barebones system and executes 'hello', a simple Hello
+World application. Adds a simple memobj between the CPU and the membus.
+
+This config file assumes that the x86 ISA was built.
+"""
+
+# import the m5 (gem5) library created when gem5 is built
+import m5
+# import all of the SimObjects
+from m5.objects import *
+
+# create the system we are going to simulate
+system = System()
+
+# Set the clock fequency of the system (and all of its children)
+system.clk_domain = SrcClockDomain()
+system.clk_domain.clock = '1GHz'
+system.clk_domain.voltage_domain = VoltageDomain()
+
+# Set up the system
+system.mem_mode = 'timing' # Use timing accesses
+system.mem_ranges = [AddrRange('512MB')] # Create an address range
+
+# Create a simple CPU
+system.cpu = TimingSimpleCPU()
+
+# Create the simple memory object
+system.memobj = SimpleMemobj()
+
+# Hook the CPU ports up to the cache
+system.cpu.icache_port = system.memobj.inst_port
+system.cpu.dcache_port = system.memobj.data_port
+
+# Create a memory bus, a coherent crossbar, in this case
+system.membus = SystemXBar()
+
+# Connect the memobj
+system.memobj.mem_side = system.membus.slave
+
+# create the interrupt controller for the CPU and connect to the membus
+system.cpu.createInterruptController()
+system.cpu.interrupts[0].pio = system.membus.master
+system.cpu.interrupts[0].int_master = system.membus.slave
+system.cpu.interrupts[0].int_slave = system.membus.master
+
+# Create a DDR3 memory controller and connect it to the membus
+system.mem_ctrl = DDR3_1600_8x8()
+system.mem_ctrl.range = system.mem_ranges[0]
+system.mem_ctrl.port = system.membus.master
+
+# Connect the system up to the membus
+system.system_port = system.membus.slave
+
+# Create a process for a simple "Hello World" application
+process = Process()
+# Set the command
+# cmd is a list which begins with the executable (like argv)
+process.cmd = ['tests/test-progs/hello/bin/x86/linux/hello']
+# Set the cpu to use the process as its workload and create thread contexts
+system.cpu.workload = process
+system.cpu.createThreads()
+
+# set up the root SimObject and start the simulation
+root = Root(full_system = False, system = system)
+# instantiate all of the objects we've created above
+m5.instantiate()
+
+print "Beginning simulation!"
+exit_event = m5.simulate()
+print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())
SimObject('SimpleObject.py')
SimObject('HelloObject.py')
+SimObject('SimpleMemobj.py')
Source('simple_object.cc')
Source('hello_object.cc')
Source('goodbye_object.cc')
+Source('simple_memobj.cc')
DebugFlag('HelloExample', "For Learning gem5 Part 2. Simple example debug flag")
+DebugFlag('SimpleMemobj', "For Learning gem5 Part 2.")
--- /dev/null
+# -*- coding: utf-8 -*-
+# Copyright (c) 2017 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+from m5.params import *
+from MemObject import MemObject
+
+class SimpleMemobj(MemObject):
+ type = 'SimpleMemobj'
+ cxx_header = "learning_gem5/part2/simple_memobj.hh"
+
+ inst_port = SlavePort("CPU side port, receives requests")
+ data_port = SlavePort("CPU side port, receives requests")
+ mem_side = MasterPort("Memory side port, sends requests")
--- /dev/null
+/*
+ * Copyright (c) 2017 Jason Lowe-Power
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Jason Lowe-Power
+ */
+
+#include "learning_gem5/part2/simple_memobj.hh"
+
+#include "debug/SimpleMemobj.hh"
+
+SimpleMemobj::SimpleMemobj(SimpleMemobjParams *params) :
+ MemObject(params),
+ instPort(params->name + ".inst_port", this),
+ dataPort(params->name + ".data_port", this),
+ memPort(params->name + ".mem_side", this),
+ blocked(false)
+{
+}
+
+BaseMasterPort&
+SimpleMemobj::getMasterPort(const std::string& if_name, PortID idx)
+{
+ panic_if(idx != InvalidPortID, "This object doesn't support vector ports");
+
+ // This is the name from the Python SimObject declaration (SimpleMemobj.py)
+ if (if_name == "mem_side") {
+ return memPort;
+ } else {
+ // pass it along to our super class
+ return MemObject::getMasterPort(if_name, idx);
+ }
+}
+
+BaseSlavePort&
+SimpleMemobj::getSlavePort(const std::string& if_name, PortID idx)
+{
+ panic_if(idx != InvalidPortID, "This object doesn't support vector ports");
+
+ // This is the name from the Python SimObject declaration in SimpleCache.py
+ if (if_name == "inst_port") {
+ return instPort;
+ } else if (if_name == "data_port") {
+ return dataPort;
+ } else {
+ // pass it along to our super class
+ return MemObject::getSlavePort(if_name, idx);
+ }
+}
+
+void
+SimpleMemobj::CPUSidePort::sendPacket(PacketPtr pkt)
+{
+ // Note: This flow control is very simple since the memobj is blocking.
+
+ panic_if(blockedPacket != nullptr, "Should never try to send if blocked!");
+
+ // If we can't send the packet across the port, store it for later.
+ if (!sendTimingResp(pkt)) {
+ blockedPacket = pkt;
+ }
+}
+
+AddrRangeList
+SimpleMemobj::CPUSidePort::getAddrRanges() const
+{
+ return owner->getAddrRanges();
+}
+
+void
+SimpleMemobj::CPUSidePort::trySendRetry()
+{
+ if (needRetry && blockedPacket == nullptr) {
+ // Only send a retry if the port is now completely free
+ needRetry = false;
+ DPRINTF(SimpleMemobj, "Sending retry req for %d\n", id);
+ sendRetryReq();
+ }
+}
+
+void
+SimpleMemobj::CPUSidePort::recvFunctional(PacketPtr pkt)
+{
+ // Just forward to the memobj.
+ return owner->handleFunctional(pkt);
+}
+
+bool
+SimpleMemobj::CPUSidePort::recvTimingReq(PacketPtr pkt)
+{
+ // Just forward to the memobj.
+ if (!owner->handleRequest(pkt)) {
+ needRetry = true;
+ return false;
+ } else {
+ return true;
+ }
+}
+
+void
+SimpleMemobj::CPUSidePort::recvRespRetry()
+{
+ // We should have a blocked packet if this function is called.
+ assert(blockedPacket != nullptr);
+
+ // Grab the blocked packet.
+ PacketPtr pkt = blockedPacket;
+ blockedPacket = nullptr;
+
+ // Try to resend it. It's possible that it fails again.
+ sendPacket(pkt);
+}
+
+void
+SimpleMemobj::MemSidePort::sendPacket(PacketPtr pkt)
+{
+ // Note: This flow control is very simple since the memobj is blocking.
+
+ panic_if(blockedPacket != nullptr, "Should never try to send if blocked!");
+
+ // If we can't send the packet across the port, store it for later.
+ if (!sendTimingReq(pkt)) {
+ blockedPacket = pkt;
+ }
+}
+
+bool
+SimpleMemobj::MemSidePort::recvTimingResp(PacketPtr pkt)
+{
+ // Just forward to the memobj.
+ return owner->handleResponse(pkt);
+}
+
+void
+SimpleMemobj::MemSidePort::recvReqRetry()
+{
+ // We should have a blocked packet if this function is called.
+ assert(blockedPacket != nullptr);
+
+ // Grab the blocked packet.
+ PacketPtr pkt = blockedPacket;
+ blockedPacket = nullptr;
+
+ // Try to resend it. It's possible that it fails again.
+ sendPacket(pkt);
+}
+
+void
+SimpleMemobj::MemSidePort::recvRangeChange()
+{
+ owner->sendRangeChange();
+}
+
+bool
+SimpleMemobj::handleRequest(PacketPtr pkt)
+{
+ if (blocked) {
+ // There is currently an outstanding request. Stall.
+ return false;
+ }
+
+ DPRINTF(SimpleMemobj, "Got request for addr %#x\n", pkt->getAddr());
+
+ // This memobj is now blocked waiting for the response to this packet.
+ blocked = true;
+
+ // Simply forward to the memory port
+ memPort.sendPacket(pkt);
+
+ return true;
+}
+
+bool
+SimpleMemobj::handleResponse(PacketPtr pkt)
+{
+ assert(blocked);
+ DPRINTF(SimpleMemobj, "Got response for addr %#x\n", pkt->getAddr());
+
+ // The packet is now done. We're about to put it in the port, no need for
+ // this object to continue to stall.
+ // We need to free the resource before sending the packet in case the CPU
+ // tries to send another request immediately (e.g., in the same callchain).
+ blocked = false;
+
+ // Simply forward to the memory port
+ if (pkt->req->isInstFetch()) {
+ instPort.sendPacket(pkt);
+ } else {
+ dataPort.sendPacket(pkt);
+ }
+
+ // For each of the cpu ports, if it needs to send a retry, it should do it
+ // now since this memory object may be unblocked now.
+ instPort.trySendRetry();
+ dataPort.trySendRetry();
+
+ return true;
+}
+
+void
+SimpleMemobj::handleFunctional(PacketPtr pkt)
+{
+ // Just pass this on to the memory side to handle for now.
+ memPort.sendFunctional(pkt);
+}
+
+AddrRangeList
+SimpleMemobj::getAddrRanges() const
+{
+ DPRINTF(SimpleMemobj, "Sending new ranges\n");
+ // Just use the same ranges as whatever is on the memory side.
+ return memPort.getAddrRanges();
+}
+
+void
+SimpleMemobj::sendRangeChange()
+{
+ instPort.sendRangeChange();
+ dataPort.sendRangeChange();
+}
+
+
+
+SimpleMemobj*
+SimpleMemobjParams::create()
+{
+ return new SimpleMemobj(this);
+}
--- /dev/null
+/*
+ * Copyright (c) 2017 Jason Lowe-Power
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Jason Lowe-Power
+ */
+
+#ifndef __LEARNING_GEM5_PART2_SIMPLE_MEMOBJ_HH__
+#define __LEARNING_GEM5_PART2_SIMPLE_MEMOBJ_HH__
+
+#include "mem/mem_object.hh"
+#include "params/SimpleMemobj.hh"
+
+/**
+ * A very simple memory object. Current implementation doesn't even cache
+ * anything it just forwards requests and responses.
+ * This memobj is fully blocking (not non-blocking). Only a single request can
+ * be outstanding at a time.
+ */
+class SimpleMemobj : public MemObject
+{
+ private:
+
+ /**
+ * Port on the CPU-side that receives requests.
+ * Mostly just forwards requests to the owner.
+ * Part of a vector of ports. One for each CPU port (e.g., data, inst)
+ */
+ class CPUSidePort : public SlavePort
+ {
+ private:
+ /// The object that owns this object (SimpleMemobj)
+ SimpleMemobj *owner;
+
+ /// True if the port needs to send a retry req.
+ bool needRetry;
+
+ /// If we tried to send a packet and it was blocked, store it here
+ PacketPtr blockedPacket;
+
+ public:
+ /**
+ * Constructor. Just calls the superclass constructor.
+ */
+ CPUSidePort(const std::string& name, SimpleMemobj *owner) :
+ SlavePort(name, owner), owner(owner), needRetry(false),
+ blockedPacket(nullptr)
+ { }
+
+ /**
+ * Send a packet across this port. This is called by the owner and
+ * all of the flow control is hanled in this function.
+ *
+ * @param packet to send.
+ */
+ void sendPacket(PacketPtr pkt);
+
+ /**
+ * Get a list of the non-overlapping address ranges the owner is
+ * responsible for. All slave ports must override this function
+ * and return a populated list with at least one item.
+ *
+ * @return a list of ranges responded to
+ */
+ AddrRangeList getAddrRanges() const override;
+
+ /**
+ * Send a retry to the peer port only if it is needed. This is called
+ * from the SimpleMemobj whenever it is unblocked.
+ */
+ void trySendRetry();
+
+ protected:
+ /**
+ * Receive an atomic request packet from the master port.
+ * No need to implement in this simple memobj.
+ */
+ Tick recvAtomic(PacketPtr pkt) override
+ { panic("recvAtomic unimpl."); }
+
+ /**
+ * Receive a functional request packet from the master port.
+ * Performs a "debug" access updating/reading the data in place.
+ *
+ * @param packet the requestor sent.
+ */
+ void recvFunctional(PacketPtr pkt) override;
+
+ /**
+ * Receive a timing request from the master port.
+ *
+ * @param the packet that the requestor sent
+ * @return whether this object can consume the packet. If false, we
+ * will call sendRetry() when we can try to receive this
+ * request again.
+ */
+ bool recvTimingReq(PacketPtr pkt) override;
+
+ /**
+ * Called by the master port if sendTimingResp was called on this
+ * slave port (causing recvTimingResp to be called on the master
+ * port) and was unsuccesful.
+ */
+ void recvRespRetry() override;
+ };
+
+ /**
+ * Port on the memory-side that receives responses.
+ * Mostly just forwards requests to the owner
+ */
+ class MemSidePort : public MasterPort
+ {
+ private:
+ /// The object that owns this object (SimpleMemobj)
+ SimpleMemobj *owner;
+
+ /// If we tried to send a packet and it was blocked, store it here
+ PacketPtr blockedPacket;
+
+ public:
+ /**
+ * Constructor. Just calls the superclass constructor.
+ */
+ MemSidePort(const std::string& name, SimpleMemobj *owner) :
+ MasterPort(name, owner), owner(owner), blockedPacket(nullptr)
+ { }
+
+ /**
+ * Send a packet across this port. This is called by the owner and
+ * all of the flow control is hanled in this function.
+ *
+ * @param packet to send.
+ */
+ void sendPacket(PacketPtr pkt);
+
+ protected:
+ /**
+ * Receive a timing response from the slave port.
+ */
+ bool recvTimingResp(PacketPtr pkt) override;
+
+ /**
+ * Called by the slave port if sendTimingReq was called on this
+ * master port (causing recvTimingReq to be called on the slave
+ * port) and was unsuccesful.
+ */
+ void recvReqRetry() override;
+
+ /**
+ * Called to receive an address range change from the peer slave
+ * port. The default implementation ignores the change and does
+ * nothing. Override this function in a derived class if the owner
+ * needs to be aware of the address ranges, e.g. in an
+ * interconnect component like a bus.
+ */
+ void recvRangeChange() override;
+ };
+
+ /**
+ * Handle the request from the CPU side
+ *
+ * @param requesting packet
+ * @return true if we can handle the request this cycle, false if the
+ * requestor needs to retry later
+ */
+ bool handleRequest(PacketPtr pkt);
+
+ /**
+ * Handle the respone from the memory side
+ *
+ * @param responding packet
+ * @return true if we can handle the response this cycle, false if the
+ * responder needs to retry later
+ */
+ bool handleResponse(PacketPtr pkt);
+
+ /**
+ * Handle a packet functionally. Update the data on a write and get the
+ * data on a read.
+ *
+ * @param packet to functionally handle
+ */
+ void handleFunctional(PacketPtr pkt);
+
+ /**
+ * Return the address ranges this memobj is responsible for. Just use the
+ * same as the next upper level of the hierarchy.
+ *
+ * @return the address ranges this memobj is responsible for
+ */
+ AddrRangeList getAddrRanges() const;
+
+ /**
+ * Tell the CPU side to ask for our memory ranges.
+ */
+ void sendRangeChange();
+
+ /// Instantiation of the CPU-side ports
+ CPUSidePort instPort;
+ CPUSidePort dataPort;
+
+ /// Instantiation of the memory-side port
+ MemSidePort memPort;
+
+ /// True if this is currently blocked waiting for a response.
+ bool blocked;
+
+ public:
+
+ /** constructor
+ */
+ SimpleMemobj(SimpleMemobjParams *params);
+
+ /**
+ * Get a master port with a given name and index. This is used at
+ * binding time and returns a reference to a protocol-agnostic
+ * base master port.
+ *
+ * @param if_name Port name
+ * @param idx Index in the case of a VectorPort
+ *
+ * @return A reference to the given port
+ */
+ BaseMasterPort& getMasterPort(const std::string& if_name,
+ PortID idx = InvalidPortID) override;
+
+ /**
+ * Get a slave port with a given name and index. This is used at
+ * binding time and returns a reference to a protocol-agnostic
+ * base master port.
+ *
+ * @param if_name Port name
+ * @param idx Index in the case of a VectorPort
+ *
+ * @return A reference to the given port
+ */
+ BaseSlavePort& getSlavePort(const std::string& if_name,
+ PortID idx = InvalidPortID) override;
+};
+
+
+#endif // __LEARNING_GEM5_PART2_SIMPLE_MEMOBJ_HH__
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