Ignore empty parameters in Verilog module instantiations

Fixes #2394

Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 8e5236639e8cc81a0c0e6369fec2ba211d99c9f2..678ce6c8759ae572dc5b7b0d5192b76aebc631b3 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1891,6 +1891,9 @@ cell_parameter:
                astbuf1->children.push_back(node);
                node->children.push_back($1);
        } |
+       '.' TOK_ID '(' ')' {
+               // just ignore empty parameters
+       } |
        '.' TOK_ID '(' expr ')' {
                AstNode *node = new AstNode(AST_PARASET);
                node->str = *$2;