hdl.ir: accept LHS signals like slices as Instance io ports.

This is unlikely to work with anything except Slice and Cat, but
there's no especially good place to enforce it. (Maybe in Instance?)

diff --git a/nmigen/hdl/ir.py b/nmigen/hdl/ir.py
index eb322820239d07cfa707fe05285c28f64d3b5ad2..a49db7749066259517d8c38a6f471d348cb99b12 100644 (file)
--- a/nmigen/hdl/ir.py
+++ b/nmigen/hdl/ir.py
@@ -373,9 +373,12 @@ class Fragment:
                 else:
                     assert defs[sig] is self
 
-        def add_io(sig):
-            assert sig not in ios
-            ios[sig] = self
+        def add_io(*sigs):
+            for sig in flatten(sigs):
+                if sig not in ios:
+                    ios[sig] = self
+                else:
+                    assert ios[sig] is self
 
         # Collect all signals we're driving (on LHS of statements), and signals we're using
         # (on RHS of statements, or in clock domains).
@@ -400,8 +403,8 @@ class Fragment:
                         subfrag.add_ports(value._lhs_signals(), dir=dir)
                         add_defs(value._lhs_signals())
                     if dir == "io":
-                        subfrag.add_ports(value, dir=dir)
-                        add_io(value)
+                        subfrag.add_ports(value._lhs_signals(), dir=dir)
+                        add_io(value._lhs_signals())
             else:
                 parent[subfrag] = self
                 level [subfrag] = level[self] + 1

diff --git a/nmigen/test/test_hdl_ir.py b/nmigen/test/test_hdl_ir.py
index 850e5f46510510cc4579a659e81a4a9db892206e..7f03a62b112fea66132fbd0f6ccdb4c6b7925463 100644 (file)
--- a/nmigen/test/test_hdl_ir.py
+++ b/nmigen/test/test_hdl_ir.py
@@ -603,7 +603,7 @@ class InstanceTestCase(FHDLTestCase):
             i_rst=self.rst,
             o_stb=self.stb,
             o_data=Cat(self.datal, self.datah),
-            io_pins=self.pins
+            io_pins=self.pins[:]
         )
         self.wrap = Fragment()
         self.wrap.add_subfragment(self.inst)