(no commit message)

diff --git a/openpower/sv/po9_encoding.mdwn b/openpower/sv/po9_encoding.mdwn
index b83989927e0876156a7e3c7b4e6b14ef349405d3..51d64c5464bb742ae3452e3909f9b03e1cd3f485 100644 (file)
--- a/openpower/sv/po9_encoding.mdwn
+++ b/openpower/sv/po9_encoding.mdwn
@@ -59,7 +59,7 @@ as UnVectoriseable because there is only one `MSR`.
 UnVectorised instructions are required to be detected as such if Prefixed
 (either SVP64 or SVP64Single) and an Illegal Instruction Trap raised.
 
-*Architectural Note: Given that a "pre-classification" Decode Phase
+*Hardware Architectural Note: Given that a "pre-classification" Decode Phase
 is required (identifying whether the Suffix - Defined Word - is
 Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional), adding
 "UnVectorised" to this phase is not unreasonable.*