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missing brackets in lhbrx
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 27 Oct 2023 10:55:38 +0000 (11:55 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 29 Oct 2023 08:54:37 +0000 (08:54 +0000)
openpower/isa/fixedloadshift.mdwn patch | blob | history

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index ba0b5d1e0ffb6c3900843b821a3342b39895c37e..504ba83998fa50cbe4d0768eac6489f0e3c365cc 100644 (file)
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -357,7 +357,7 @@ Description:
     register RB shifted by (SH+1), and (RA|0).
 
     Bits 0:7 of the halfword in storage addressed by EA are
-    loaded into RT 56:63. Bits 8:15 of the halfword in storage
+    loaded into RT[56:63]. Bits 8:15 of the halfword in storage
     addressed by EA are loaded into RT[48:55].
     RT[0:47] are set to 0.