+2003-02-19 Kazu Hirata <kazu@cs.umass.edu>
+
+ * config/h8300/h8300.c (output_logical_op): Optimize or.l when
+ ORing with 0xffff??00 with the highest bit of the ?? part set.
+ (compute_logical_op_length): Update.
+ (compute_logical_op_cc): Likewise.
+
2003-02-19 Josef Zlomek <zlomekj@suse.cz>
* bb-reorder.c (find_traces_1_round): Fixed condition for small
using multiple insns. */
if ((TARGET_H8300H || TARGET_H8300S)
&& w0 != 0 && w1 != 0
- && !(lower_half_easy_p && upper_half_easy_p))
+ && !(lower_half_easy_p && upper_half_easy_p)
+ && !(code == IOR && w1 == 0xffff
+ && (w0 & 0x8000) != 0 && lower_half_easy_p))
{
sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
output_asm_insn (insn_buf, operands);
output_asm_insn ((code == AND)
? "sub.w\t%e0,%e0" : "not.w\t%e0",
operands);
+ else if ((TARGET_H8300H || TARGET_H8300S)
+ && code == IOR
+ && w1 == 0xffff
+ && (w0 & 0x8000) != 0)
+ {
+ output_asm_insn ("exts.l\t%S0", operands);
+ }
else if ((TARGET_H8300H || TARGET_H8300S)
&& code == AND
&& w1 == 0xff00)
using multiple insns. */
if ((TARGET_H8300H || TARGET_H8300S)
&& w0 != 0 && w1 != 0
- && !(lower_half_easy_p && upper_half_easy_p))
+ && !(lower_half_easy_p && upper_half_easy_p)
+ && !(code == IOR && w1 == 0xffff
+ && (w0 & 0x8000) != 0 && lower_half_easy_p))
{
if (REG_P (operands[2]))
length += 4;
{
length += 2;
}
+ else if ((TARGET_H8300H || TARGET_H8300S)
+ && code == IOR
+ && w1 == 0xffff
+ && (w0 & 0x8000) != 0)
+ {
+ length += 2;
+ }
else if ((TARGET_H8300H || TARGET_H8300S)
&& code == AND
&& w1 == 0xff00)
using multiple insns. */
if ((TARGET_H8300H || TARGET_H8300S)
&& w0 != 0 && w1 != 0
- && !(lower_half_easy_p && upper_half_easy_p))
+ && !(lower_half_easy_p && upper_half_easy_p)
+ && !(code == IOR && w1 == 0xffff
+ && (w0 & 0x8000) != 0 && lower_half_easy_p))
{
cc = CC_SET_ZNV;
}
+ else
+ {
+ if ((TARGET_H8300H || TARGET_H8300S)
+ && code == IOR
+ && w1 == 0xffff
+ && (w0 & 0x8000) != 0)
+ {
+ cc = CC_SET_ZNV;
+ }
+ }
break;
default:
abort ();