arm: Bootloader fix for v8 over 16 cores

Previous code used a smaller 4 bit mask to test the MPIDR-EL1 register.
The bitmask was extended to support greater than 16 cores.

diff --git a/system/arm/aarch64_bootloader/boot.S b/system/arm/aarch64_bootloader/boot.S
index 78d9710d4336bbaed15aa25462deec50fd95e756..933d7ee8a9c27478972995e755c0cd88c14050ff 100644 (file)
--- a/system/arm/aarch64_bootloader/boot.S
+++ b/system/arm/aarch64_bootloader/boot.S
@@ -34,8 +34,12 @@ _start:
          * registers.
          */
         mrs    x0, mpidr_el1
-        tst    x0, #15
-        b.ne   1f                              // secondary CPU
+        // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
+        // Test the the MPIDR_EL1 register against 0xff00ffffff to
+        // extract the primary CPU.
+        ldr x1, =0xff00ffffff
+        tst x0, x1                    // check for cpuid==zero
+        b.ne   1f                                    // secondary CPU
 
         ldr    x1, =GIC_DIST_BASE              // GICD_CTLR
         mov    w0, #3                          // EnableGrp0 | EnableGrp1
@@ -77,8 +81,13 @@ start_ns:
         mov    x3, xzr
 
         mrs    x4, mpidr_el1
-        tst    x4, #15
-        b.eq   2f
+        // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
+        // Test the the MPIDR_EL1 register against 0xff00ffffff to
+        // extract the primary CPU.
+        ldr x1, =0xff00ffffff
+        tst x4, x1                    // check for cpuid==zero
+        mov x1, xzr                   // load previous 'xzr' value back to x1
+        b.eq   2f                                    // secondary CPU
 
         /*
          * Secondary CPUs