$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_init3.vh))
+EXTRA_OBJS += techlibs/gowin/brams_init.mk
+.SECONDARY: techlibs/gowin/brams_init.mk
+
+techlibs/gowin/brams_init.mk: techlibs/gowin/brams_init.py
+ $(Q) mkdir -p techlibs/gowin
+ $(P) python3 $<
+ $(Q) touch $@
+
+techlibs/gowin/bram_init_16.vh: techlibs/gowin/brams_init.mk
+$(eval $(call add_gen_share_file,share/gowin,techlibs/gowin/bram_init_16.vh))
bram $__GW1NR_SDP
-# uncomment when done
-# init 1
+ init 1
abits 10 @a10d18
dbits 16 @a10d18
abits 11 @a11d9
--- /dev/null
+#!/usr/bin/env python3
+
+with open("techlibs/gowin/bram_init_16.vh", "w") as f:
+ for i in range(0, 0x40):
+ low = i << 8
+ hi = ((i+1) << 8)-1
+ snippet = "INIT[%d:%d]" % (hi, low)
+ print(".INIT_RAM_%02X({%s})," % (i, snippet), file=f)
generate if (CFG_DBITS == 1) begin
SDP #(
+ `include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(1),
.BIT_WIDTH_1(1),
);
end else if (CFG_DBITS == 2) begin
SDP #(
+ `include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(2),
.BIT_WIDTH_1(2),
);
end else if (CFG_DBITS <= 4) begin
SDP #(
+ `include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(4),
.BIT_WIDTH_1(4),
);
end else if (CFG_DBITS <= 8) begin
SDP #(
+ `include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(8),
.BIT_WIDTH_1(8),
);
end else if (CFG_DBITS <= 16) begin
SDP #(
+ `include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(16),
.BIT_WIDTH_1(16),
if (check_label("vout"))
{
if (!vout_file.empty() || help_mode)
- run(stringf("write_verilog -nohex -decimal -attr2comment -defparam -renameprefix gen %s",
+ run(stringf("write_verilog -decimal -attr2comment -defparam -renameprefix gen %s",
help_mode ? "<file-name>" : vout_file.c_str()));
}
}