radeonsi/gfx9: disable features that don't work

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index c6d2381b122556a51097e8537371f4149e591413..dbcfd58a4bc8d390a14996be8df45b4d528f9d2e 100644 (file)
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1625,7 +1625,9 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
                 * Use the staging texture for uploads if the underlying BO
                 * is busy.
                 */
-               if (!rtex->surface.is_linear)
+               /* TODO: Linear CPU mipmap addressing is broken on GFX9: */
+               if (!rtex->surface.is_linear ||
+                   (rctx->chip_class == GFX9 && level))
                        use_staging_texture = true;
                else if (usage & PIPE_TRANSFER_READ)
                        use_staging_texture =
@@ -2632,6 +2634,10 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
        if (rctx->render_cond)
                return;
 
+       /* TODO: fix CMASK and DCC fast clear */
+       if (rctx->chip_class >= GFX9)
+               return;
+
        for (i = 0; i < fb->nr_cbufs; i++) {
                struct r600_texture *tex;
                unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index d4f3736533a2ec9e395d89f104cf423dc991002e..580781bd4cb280771a30b2da5bde34da20b09a6d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -4590,8 +4590,9 @@ static void tex_fetch_args(
         * The sample index should be adjusted as follows:
         *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
         */
-       if (target == TGSI_TEXTURE_2D_MSAA ||
-           target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
+       if (ctx->screen->b.chip_class <= VI && /* TODO: fix FMASK on GFX9 */
+           (target == TGSI_TEXTURE_2D_MSAA ||
+            target == TGSI_TEXTURE_2D_ARRAY_MSAA)) {
                struct lp_build_context *uint_bld = &bld_base->uint_bld;
                struct lp_build_emit_data txf_emit_data = *emit_data;
                LLVMValueRef txf_address[4];

diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index 7965b461dce7943546cfd0c80f1135727fbc195c..efc9452e9f9a6f80c4a1cef49aacba4e15ff9069 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -834,7 +834,9 @@ static void emit_declaration(struct lp_build_tgsi_context *bld_base,
                         *
                         * LLVM 3.8 crashes with this.
                         */
-                       if (HAVE_LLVM >= 0x0309 && array_size > 16) {
+                       if ((HAVE_LLVM >= 0x0309 && array_size > 16) ||
+                           /* TODO: VGPR indexing is buggy on GFX9. */
+                           ctx->screen->b.chip_class == GFX9) {
                                array_alloca = LLVMBuildAlloca(builder,
                                        LLVMArrayType(bld_base->base.vec_type,
                                                      array_size), "array");

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index c4063a8a8d6d5dca0d41dc11a5424db429a40270..d2a1f4bf85c491090d9cdba9cbf14131bddbfc7f 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2198,7 +2198,8 @@ static void si_initialize_color_surface(struct si_context *sctx,
                                S_028C74_NUM_FRAGMENTS(log_samples);
 
                if (rtex->fmask.size) {
-                       color_info |= S_028C70_COMPRESSION(1);
+                        /* TODO: fix FMASK on GFX9: */
+                       color_info |= S_028C70_COMPRESSION(sctx->b.chip_class <= VI);
                        unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
 
                        if (sctx->b.chip_class == SI) {