+++ /dev/null
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
-acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_cpu_frequency=500
-boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-e820_table=system.e820_table
-init_param=0
-intel_mp_pointer=system.intel_mp_pointer
-intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-load_addr_mask=18446744073709551615
-mem_mode=atomic
-physmem=system.physmem
-readfile=tests/halt.sh
-smbios_table=system.smbios_table
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-
-[system.acpi_description_table_pointer]
-type=X86ACPIRSDP
-children=xsdt
-oem_id=
-revision=2
-rsdt=Null
-xsdt=system.acpi_description_table_pointer.xsdt
-
-[system.acpi_description_table_pointer.xsdt]
-type=X86ACPIXSDT
-creator_id=
-creator_revision=0
-entries=
-oem_id=
-oem_revision=0
-oem_table_id=
-
-[system.bridge]
-type=Bridge
-delay=50000
-filter_ranges_a=0:1152921504606846975
-filter_ranges_b=0:134217727
-nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
-write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[1]
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache tracer
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu.tracer
-width=1
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-system=system
-port=system.cpu.dtb_walker_cache.cpu_side
-
-[system.cpu.dtb_walker_cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dtb.walker.port
-mem_side=system.toL2Bus.port[4]
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu.interrupts]
-type=X86LocalApic
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=1000
-platform=system.pc
-system=system
-int_port=system.membus.port[5]
-pio=system.membus.port[4]
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-system=system
-port=system.cpu.itb_walker_cache.cpu_side
-
-[system.cpu.itb_walker_cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.itb.walker.port
-mem_side=system.toL2Bus.port[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.e820_table]
-type=X86E820Table
-children=entries0 entries1
-entries=system.e820_table.entries0 system.e820_table.entries1
-
-[system.e820_table.entries0]
-type=X86E820Entry
-addr=0
-range_type=2
-size=1048576
-
-[system.e820_table.entries1]
-type=X86E820Entry
-addr=1048576
-range_type=1
-size=133169152
-
-[system.intel_mp_pointer]
-type=X86IntelMPFloatingPointer
-default_config=0
-imcr_present=true
-spec_rev=4
-
-[system.intel_mp_table]
-type=X86IntelMPConfigTable
-children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
-base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
-ext_entries=system.intel_mp_table.ext_entries
-local_apic=4276092928
-oem_id=
-oem_table_addr=0
-oem_table_size=0
-product_id=
-spec_rev=4
-
-[system.intel_mp_table.base_entries00]
-type=X86IntelMPProcessor
-bootstrap=true
-enable=true
-family=0
-feature_flags=0
-local_apic_id=0
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries01]
-type=X86IntelMPIOAPIC
-address=4273995776
-enable=true
-id=1
-version=17
-
-[system.intel_mp_table.base_entries02]
-type=X86IntelMPBus
-bus_id=0
-bus_type=ISA
-
-[system.intel_mp_table.base_entries03]
-type=X86IntelMPBus
-bus_id=1
-bus_type=PCI
-
-[system.intel_mp_table.base_entries04]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=16
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=16
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries05]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries06]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=2
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries07]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries08]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=1
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries09]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries10]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=3
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries11]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries12]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=4
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries13]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries14]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=5
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries15]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries16]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=6
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries17]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries18]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=7
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries19]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries20]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=8
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries21]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries22]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=9
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries23]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries24]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=10
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries25]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries26]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=11
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries27]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries28]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=12
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries29]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries30]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=13
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries31]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries32]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=14
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.ext_entries]
-type=X86IntelMPBusHierarchy
-bus_id=0
-parent_bus=1
-subtractive_decode=true
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=true
-width=64
-default=system.pc.pciconfig.pio
-port=system.bridge.side_a system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma
-
-[system.iocache]
-type=BaseCache
-addr_range=0:134217727
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[18]
-mem_side=system.membus.port[2]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[3]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
-
-[system.membus.badaddr_responder]
-type=IsaFake
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.pc]
-type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal
-intrctrl=system.intrctrl
-system=system
-
-[system.pc.behind_pci]
-type=IsaFake
-pio_addr=9223372036854779128
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[12]
-
-[system.pc.com_1]
-type=Uart8250
-pio_addr=9223372036854776824
-pio_latency=1000
-platform=system.pc
-system=system
-terminal=system.pc.terminal
-pio=system.iobus.port[13]
-
-[system.pc.fake_com_2]
-type=IsaFake
-pio_addr=9223372036854776568
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[14]
-
-[system.pc.fake_com_3]
-type=IsaFake
-pio_addr=9223372036854776808
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[15]
-
-[system.pc.fake_com_4]
-type=IsaFake
-pio_addr=9223372036854776552
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[16]
-
-[system.pc.fake_floppy]
-type=IsaFake
-pio_addr=9223372036854776818
-pio_latency=1000
-pio_size=2
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[17]
-
-[system.pc.i_dont_exist]
-type=IsaFake
-pio_addr=9223372036854775936
-pio_latency=1000
-pio_size=1
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[11]
-
-[system.pc.pciconfig]
-type=PciConfigAll
-bus=0
-pio_latency=1
-platform=system.pc
-size=16777216
-system=system
-pio=system.iobus.default
-
-[system.pc.south_bridge]
-type=SouthBridge
-children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
-cmos=system.pc.south_bridge.cmos
-dma1=system.pc.south_bridge.dma1
-int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6
-io_apic=system.pc.south_bridge.io_apic
-keyboard=system.pc.south_bridge.keyboard
-pic1=system.pc.south_bridge.pic1
-pic2=system.pc.south_bridge.pic2
-pio_latency=1000
-pit=system.pc.south_bridge.pit
-platform=system.pc
-speaker=system.pc.south_bridge.speaker
-
-[system.pc.south_bridge.cmos]
-type=Cmos
-int_pin=system.pc.south_bridge.int_lines2.source
-pio_addr=9223372036854775920
-pio_latency=1000
-platform=system.pc
-system=system
-time=Sun Jan 1 00:00:00 2012
-pio=system.iobus.port[1]
-
-[system.pc.south_bridge.dma1]
-type=I8237
-pio_addr=9223372036854775808
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[2]
-
-[system.pc.south_bridge.ide]
-type=IdeController
-children=disks0 disks1
-BAR0=496
-BAR0LegacyIO=true
-BAR0Size=8
-BAR1=1012
-BAR1LegacyIO=true
-BAR1Size=3
-BAR2=368
-BAR2LegacyIO=true
-BAR2Size=8
-BAR3=884
-BAR3LegacyIO=true
-BAR3Size=3
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=14
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=128
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=0
-disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
-io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=4
-pci_func=0
-pio_latency=1000
-platform=system.pc
-system=system
-config=system.iobus.port[19]
-dma=system.iobus.port[20]
-pio=system.iobus.port[3]
-
-[system.pc.south_bridge.ide.disks0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks0.image
-
-[system.pc.south_bridge.ide.disks0.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
-read_only=true
-
-[system.pc.south_bridge.ide.disks1]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks1.image
-
-[system.pc.south_bridge.ide.disks1.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks1.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks1.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
-read_only=true
-
-[system.pc.south_bridge.int_lines0]
-type=X86IntLine
-children=sink source
-sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.int_lines0.source
-
-[system.pc.south_bridge.int_lines0.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=0
-
-[system.pc.south_bridge.int_lines0.source]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.int_lines1]
-type=X86IntLine
-children=sink source
-sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.int_lines1.source
-
-[system.pc.south_bridge.int_lines1.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=2
-
-[system.pc.south_bridge.int_lines1.source]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.int_lines2]
-type=X86IntLine
-children=sink source
-sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.int_lines2.source
-
-[system.pc.south_bridge.int_lines2.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic2
-number=0
-
-[system.pc.south_bridge.int_lines2.source]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.int_lines3]
-type=X86IntLine
-children=sink source
-sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.int_lines3.source
-
-[system.pc.south_bridge.int_lines3.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=0
-
-[system.pc.south_bridge.int_lines3.source]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.int_lines4]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.int_lines3.source
-
-[system.pc.south_bridge.int_lines4.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=2
-
-[system.pc.south_bridge.int_lines5]
-type=X86IntLine
-children=sink source
-sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.int_lines5.source
-
-[system.pc.south_bridge.int_lines5.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=1
-
-[system.pc.south_bridge.int_lines5.source]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.int_lines6]
-type=X86IntLine
-children=sink source
-sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.int_lines6.source
-
-[system.pc.south_bridge.int_lines6.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=12
-
-[system.pc.south_bridge.int_lines6.source]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.io_apic]
-type=I82094AA
-apic_id=1
-external_int_pic=system.pc.south_bridge.pic1
-int_latency=1000
-pio_addr=4273995776
-pio_latency=1000
-platform=system.pc
-system=system
-int_port=system.iobus.port[10]
-pio=system.iobus.port[9]
-
-[system.pc.south_bridge.keyboard]
-type=I8042
-command_port=9223372036854775908
-data_port=9223372036854775904
-keyboard_int_pin=system.pc.south_bridge.int_lines5.source
-mouse_int_pin=system.pc.south_bridge.int_lines6.source
-pio_addr=0
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[4]
-
-[system.pc.south_bridge.pic1]
-type=I8259
-mode=I8259Master
-output=system.pc.south_bridge.int_lines0.source
-pio_addr=9223372036854775840
-pio_latency=1000
-platform=system.pc
-slave=system.pc.south_bridge.pic2
-system=system
-pio=system.iobus.port[5]
-
-[system.pc.south_bridge.pic2]
-type=I8259
-mode=I8259Slave
-output=system.pc.south_bridge.int_lines1.source
-pio_addr=9223372036854775968
-pio_latency=1000
-platform=system.pc
-slave=Null
-system=system
-pio=system.iobus.port[6]
-
-[system.pc.south_bridge.pit]
-type=I8254
-int_pin=system.pc.south_bridge.int_lines3.source
-pio_addr=9223372036854775872
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[7]
-
-[system.pc.south_bridge.speaker]
-type=PcSpeaker
-i8254=system.pc.south_bridge.pit
-pio_addr=9223372036854775905
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[8]
-
-[system.pc.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
-[system.smbios_table]
-type=X86SMBiosSMBiosTable
-children=structures
-major_version=2
-minor_version=5
-structures=system.smbios_table.structures
-
-[system.smbios_table.structures]
-type=X86SMBiosBiosInformation
-characteristic_ext_bytes=
-characteristics=
-emb_cont_firmware_major=0
-emb_cont_firmware_minor=0
-major=0
-minor=0
-release_date=06/08/2008
-rom_size=0
-starting_addr_segment=0
-vendor=
-version=
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
-
+++ /dev/null
-warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
-warn: Reading current count from inactive timer.
-For more information see: http://www.m5sim.org/warn/1ea2be46
-warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Don't know what interrupt to clear for console.
-For more information see: http://www.m5sim.org/warn/7fe1004f
-warn: instruction 'fxsave' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
-warn: Tried to clear PCI interrupt 14
-For more information see: http://www.m5sim.org/warn/77378d57
-warn: Unknown mouse command 0xe1.
-For more information see: http://www.m5sim.org/warn/2447512a
-warn: instruction 'wbinvd' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
-hack: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Feb 26 2011 16:13:31
-M5 revision 412ef0f728a5 8092 default qtip tip updatefsstats.patch
-M5 started Feb 26 2011 16:13:35
-M5 executing on burrito
-command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
- 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5112051446000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 2446370 # Simulator instruction rate (inst/s)
-host_mem_usage 368136 # Number of bytes of host memory used
-host_seconds 166.22 # Real time elapsed on the host
-host_tick_rate 30755543746 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 406624458 # Number of instructions simulated
-sim_seconds 5.112051 # Number of seconds simulated
-sim_ticks 5112051446000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses::0 13367989 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13367989 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::0 12059464 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 12059464 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::0 0.097885 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 1308525 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1308525 # number of ReadReq misses
-system.cpu.dcache.WriteReq_accesses::0 8403116 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 8403116 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::0 8086815 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 8086815 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::0 0.037641 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 316301 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 316301 # number of WriteReq misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 12.417813 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 21771105 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 21771105 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 20146279 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 20146279 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.074632 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 1624826 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1624826 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999999 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 511.999375 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses::0 21771105 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 21771105 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 20146279 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 20146279 # number of overall hits
-system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0 0.074632 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0 1624826 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 1624826 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 1622039 # number of replacements
-system.cpu.dcache.sampled_refs 1622551 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.999375 # Cycle average of tags in use
-system.cpu.dcache.total_refs 20148535 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 1526505 # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_accesses::1 21821 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 21821 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_hits::1 12006 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 12006 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.449796 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_misses::1 9815 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 9815 # number of ReadReq misses
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.avg_refs 1.388452 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::1 21821 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 21821 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::1 12006 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 12006 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::1 0.449796 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::1 9815 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 9815 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
-system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.occ_%::1 0.313148 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_blocks::1 5.010366 # Average occupied blocks per context
-system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::1 21821 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 21821 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::1 12006 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 12006 # number of overall hits
-system.cpu.dtb_walker_cache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::1 0.449796 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::1 9815 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total 9815 # number of overall misses
-system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dtb_walker_cache.replacements 8629 # number of replacements
-system.cpu.dtb_walker_cache.sampled_refs 8642 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dtb_walker_cache.tagsinuse 5.010366 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs 11999 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5100489496500 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.writebacks 2437 # number of writebacks
-system.cpu.icache.ReadReq_accesses::0 254189385 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 254189385 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits::0 253396964 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 253396964 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_rate::0 0.003117 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0 792421 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 792421 # number of ReadReq misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 319.778505 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses::0 254189385 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 254189385 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.icache.demand_hits::0 253396964 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 253396964 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0 0.003117 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.demand_misses::0 792421 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 792421 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.997320 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 510.627884 # Average occupied blocks per context
-system.cpu.icache.overall_accesses::0 254189385 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 254189385 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 253396964 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 253396964 # number of overall hits
-system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0 0.003117 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.overall_misses::0 792421 # number of overall misses
-system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 792421 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 791902 # number of replacements
-system.cpu.icache.sampled_refs 792414 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 510.627884 # Cycle average of tags in use
-system.cpu.icache.total_refs 253396964 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 148756026000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 809 # number of writebacks
-system.cpu.idle_fraction 0.955646 # Percentage of idle cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::1 12217 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total 12217 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_hits::1 7611 # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total 7611 # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.377016 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_misses::1 4606 # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total 4606 # number of ReadReq misses
-system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.avg_refs 2.010607 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::1 12219 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total 12219 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::1 7613 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total 7613 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::1 0.376954 # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::1 4606 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total 4606 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.itb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
-system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.occ_%::1 0.188799 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.occ_blocks::1 3.020778 # Average occupied blocks per context
-system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::1 12219 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total 12219 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::1 7613 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total 7613 # number of overall hits
-system.cpu.itb_walker_cache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::1 0.376954 # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::1 4606 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total 4606 # number of overall misses
-system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.itb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.itb_walker_cache.replacements 3761 # number of replacements
-system.cpu.itb_walker_cache.sampled_refs 3771 # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.itb_walker_cache.tagsinuse 3.020778 # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs 7582 # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5105305893500 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.writebacks 603 # number of writebacks
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
-system.cpu.numCycles 10224102915 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 453482144.002058 # Number of busy cycles
-system.cpu.num_conditional_control_insts 42460207 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 9770620770.997942 # Number of idle cycles
-system.cpu.num_insts 406624458 # Number of instructions executed
-system.cpu.num_int_alu_accesses 391833838 # Number of integer alu accesses
-system.cpu.num_int_insts 391833838 # number of integer instructions
-system.cpu.num_int_register_reads 836347889 # number of times the integer registers were read
-system.cpu.num_int_register_writes 419160873 # number of times the integer registers were written
-system.cpu.num_load_insts 29720540 # Number of load instructions
-system.cpu.num_mem_refs 38133606 # number of memory refs
-system.cpu.num_store_insts 8413066 # Number of store instructions
-system.iocache.ReadReq_accesses::1 909 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses::1 909 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
-system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 47629 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 47629 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47629 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.occ_%::1 0.002653 # Average percentage of cache occupancy
-system.iocache.occ_blocks::1 0.042448 # Average occupied blocks per context
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 47629 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 47629 # number of overall misses
-system.iocache.overall_misses::total 47629 # number of overall misses
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.replacements 47574 # number of replacements
-system.iocache.sampled_refs 47590 # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0.042448 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 4994772176509 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 46667 # number of writebacks
-system.l2c.ReadExReq_accesses::0 314040 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 314040 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_hits::0 169169 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 169169 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_rate::0 0.461314 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 144871 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 144871 # number of ReadExReq misses
-system.l2c.ReadReq_accesses::0 2100261 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 10262 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2110523 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits::0 2044272 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 10235 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2054507 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0 0.026658 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.002631 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.029289 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 55989 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 27 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 56016 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses::0 1821 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1821 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_hits::0 24 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_rate::0 0.986820 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 1797 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1797 # number of UpgradeReq misses
-system.l2c.Writeback_accesses::0 1530354 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 1530354 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 1530354 # number of Writeback hits
-system.l2c.Writeback_hits::total 1530354 # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 16.953097 # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 2414301 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 10262 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2424563 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.demand_hits::0 2213441 # number of demand (read+write) hits
-system.l2c.demand_hits::1 10235 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2223676 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.083196 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.002631 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.085827 # miss rate for demand accesses
-system.l2c.demand_misses::0 200860 # number of demand (read+write) misses
-system.l2c.demand_misses::1 27 # number of demand (read+write) misses
-system.l2c.demand_misses::total 200887 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.147971 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.414180 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 9697.448079 # Average occupied blocks per context
-system.l2c.occ_blocks::1 27143.733047 # Average occupied blocks per context
-system.l2c.overall_accesses::0 2414301 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 10262 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2424563 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 2213441 # number of overall hits
-system.l2c.overall_hits::1 10235 # number of overall hits
-system.l2c.overall_hits::total 2223676 # number of overall hits
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.083196 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.002631 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.085827 # miss rate for overall accesses
-system.l2c.overall_misses::0 200860 # number of overall misses
-system.l2c.overall_misses::1 27 # number of overall misses
-system.l2c.overall_misses::total 200887 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 164351 # number of replacements
-system.l2c.sampled_refs 196384 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 36841.181126 # Cycle average of tags in use
-system.l2c.total_refs 3329317 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 144194 # number of writebacks
-system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-
----------- End Simulation Statistics ----------
+++ /dev/null
-Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007\r
-Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
-BIOS-provided physical RAM map:\r
- BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)\r
- BIOS-e820: 0000000000100000 - 0000000008000000 (usable)\r
-end_pfn_map = 32768\r
-kernel direct mapping tables up to 8000000 @ 100000-102000\r
-DMI 2.5 present.\r
-Zone PFN ranges:\r
- DMA 256 -> 4096\r
- DMA32 4096 -> 1048576\r
- Normal 1048576 -> 1048576\r
-early_node_map[1] active PFN ranges\r
- 0: 256 -> 32768\r
-Intel MultiProcessor Specification v1.4\r
-MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000\r
-Processor #0 (Bootup-CPU)\r
-I/O APIC #1 at 0xFEC00000.\r
-Setting APIC routing to flat\r
-Processors: 1\r
-Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)\r
-Built 1 zonelists. Total pages: 30458\r
-Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
-Initializing CPU#0\r
-PID hash table entries: 512 (order: 9, 4096 bytes)\r
-time.c: Detected 1999.998 MHz processor.\r
-Console: colour dummy device 80x25\r
-console handover: boot [earlyser0] -> real [ttyS0]\r
-Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)\r
-Checking aperture...\r
-Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)\r
-Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
-Mount-cache hash table entries: 256\r
-CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
-CPU: L2 Cache: 1024K (64 bytes/line)\r
-CPU: Fake M5 x86_64 CPU stepping 01\r
-ACPI: Core revision 20070126\r
-ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]\r
-ACPI: Unable to load the System Description Tables\r
-Using local APIC timer interrupts.\r
-result 7812490\r
-Detected 7.812 MHz APIC timer.\r
-NET: Registered protocol family 16\r
-PCI: Using configuration type 1\r
-ACPI: Interpreter disabled.\r
-Linux Plug and Play Support v0.97 (c) Adam Belay\r
-pnp: PnP ACPI: disabled\r
-SCSI subsystem initialized\r
-usbcore: registered new interface driver usbfs\r
-usbcore: registered new interface driver hub\r
-usbcore: registered new device driver usb\r
-PCI: Probing PCI hardware\r
-PCI-GART: No AMD northbridge found.\r
-NET: Registered protocol family 2\r
-Time: tsc clocksource has been installed.\r
-IP route cache hash table entries: 1024 (order: 1, 8192 bytes)\r
-TCP established hash table entries: 4096 (order: 4, 65536 bytes)\r
-TCP bind hash table entries: 4096 (order: 3, 32768 bytes)\r
-TCP: Hash tables configured (established 4096 bind 4096)\r
-TCP reno registered\r
-Total HugeTLB memory allocated, 0\r
-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).\r
-io scheduler noop registered\r
-io scheduler deadline registered\r
-io scheduler cfq registered (default)\r
-Real Time Clock Driver v1.12ac\r
-Linux agpgart interface v0.102 (c) Dave Jones\r
-Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled\r
-serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250\r
-floppy0: no floppy controllers found\r
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize\r
-loop: module loaded\r
-Intel(R) PRO/1000 Network Driver - version 7.3.20-k2\r
-Copyright (c) 1999-2006 Intel Corporation.\r
-e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI\r
-e100: Copyright(c) 1999-2006 Intel Corporation\r
-forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.\r
-tun: Universal TUN/TAP device driver, 1.6\r
-tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>\r
-netconsole: not configured, aborting\r
-Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2\r
-ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx\r
-PIIX4: IDE controller at PCI slot 0000:00:04.0\r
-PCI: Enabling device 0000:00:04.0 (0000 -> 0001)\r
-PIIX4: chipset revision 0\r
-PIIX4: not 100% native mode: will probe irqs later\r
- ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA\r
- ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA\r
-hda: M5 IDE Disk, ATA DISK drive\r
-hdb: M5 IDE Disk, ATA DISK drive\r
-ide0 at 0x1f0-0x1f7,0x3f6 on irq 14\r
-hda: max request size: 128KiB\r
-hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)\r
- hda: hda1\r
-hdb: max request size: 128KiB\r
-hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)\r
- hdb: unknown partition table\r
-megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)\r
-megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)\r
-megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007\r
-Fusion MPT base driver 3.04.04\r
-Copyright (c) 1999-2007 LSI Logic Corporation\r
-Fusion MPT SPI Host driver 3.04.04\r
-Fusion MPT SAS Host driver 3.04.04\r
-ieee1394: raw1394: /dev/raw1394 device initialized\r
-USB Universal Host Controller Interface driver v3.0\r
-usbcore: registered new interface driver usblp\r
-drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver\r
-Initializing USB Mass Storage driver...\r
-usbcore: registered new interface driver usb-storage\r
-USB Mass Storage support registered.\r
-PNP: No PS/2 controller found. Probing ports directly.\r
-serio: i8042 KBD port at 0x60,0x64 irq 1\r
-serio: i8042 AUX port at 0x60,0x64 irq 12\r
-mice: PS/2 mouse device common for all mice\r
-input: AT Translated Set 2 keyboard as /class/input/input0\r
-device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com\r
-input: PS/2 Generic Mouse as /class/input/input1\r
-usbcore: registered new interface driver usbhid\r
-drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver\r
-oprofile: using timer interrupt.\r
-TCP cubic registered\r
-NET: Registered protocol family 1\r
-NET: Registered protocol family 10\r
-IPv6 over IPv4 tunneling driver\r
-NET: Registered protocol family 17\r
-EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended\r
-VFS: Mounted root (ext2 filesystem).\r
-Freeing unused kernel memory: 232k freed\r
-\rINIT: version 2.86 booting\r\r
-mounting filesystems...\r
-loading script...\r
+++ /dev/null
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
-acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_cpu_frequency=500
-boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-e820_table=system.e820_table
-init_param=0
-intel_mp_pointer=system.intel_mp_pointer
-intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-load_addr_mask=18446744073709551615
-mem_mode=timing
-physmem=system.physmem
-readfile=tests/halt.sh
-smbios_table=system.smbios_table
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-
-[system.acpi_description_table_pointer]
-type=X86ACPIRSDP
-children=xsdt
-oem_id=
-revision=2
-rsdt=Null
-xsdt=system.acpi_description_table_pointer.xsdt
-
-[system.acpi_description_table_pointer.xsdt]
-type=X86ACPIXSDT
-creator_id=
-creator_revision=0
-entries=
-oem_id=
-oem_revision=0
-oem_table_id=
-
-[system.bridge]
-type=Bridge
-delay=50000
-filter_ranges_a=0:1152921504606846975
-filter_ranges_b=0:134217727
-nack_delay=4000
-req_size_a=16
-req_size_b=16
-resp_size_a=16
-resp_size_b=16
-write_ack=false
-side_a=system.iobus.port[0]
-side_b=system.membus.port[1]
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache tracer
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-profile=0
-progress_interval=0
-system=system
-tracer=system.cpu.tracer
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-system=system
-port=system.cpu.dtb_walker_cache.cpu_side
-
-[system.cpu.dtb_walker_cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dtb.walker.port
-mem_side=system.toL2Bus.port[4]
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=8
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu.interrupts]
-type=X86LocalApic
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=1000
-platform=system.pc
-system=system
-int_port=system.membus.port[5]
-pio=system.membus.port[4]
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-system=system
-port=system.cpu.itb_walker_cache.cpu_side
-
-[system.cpu.itb_walker_cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.itb.walker.port
-mem_side=system.toL2Bus.port[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.e820_table]
-type=X86E820Table
-children=entries0 entries1
-entries=system.e820_table.entries0 system.e820_table.entries1
-
-[system.e820_table.entries0]
-type=X86E820Entry
-addr=0
-range_type=2
-size=1048576
-
-[system.e820_table.entries1]
-type=X86E820Entry
-addr=1048576
-range_type=1
-size=133169152
-
-[system.intel_mp_pointer]
-type=X86IntelMPFloatingPointer
-default_config=0
-imcr_present=true
-spec_rev=4
-
-[system.intel_mp_table]
-type=X86IntelMPConfigTable
-children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
-base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
-ext_entries=system.intel_mp_table.ext_entries
-local_apic=4276092928
-oem_id=
-oem_table_addr=0
-oem_table_size=0
-product_id=
-spec_rev=4
-
-[system.intel_mp_table.base_entries00]
-type=X86IntelMPProcessor
-bootstrap=true
-enable=true
-family=0
-feature_flags=0
-local_apic_id=0
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries01]
-type=X86IntelMPIOAPIC
-address=4273995776
-enable=true
-id=1
-version=17
-
-[system.intel_mp_table.base_entries02]
-type=X86IntelMPBus
-bus_id=0
-bus_type=ISA
-
-[system.intel_mp_table.base_entries03]
-type=X86IntelMPBus
-bus_id=1
-bus_type=PCI
-
-[system.intel_mp_table.base_entries04]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=16
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=16
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries05]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries06]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=2
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries07]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries08]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=1
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries09]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries10]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=3
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries11]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries12]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=4
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries13]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries14]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=5
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries15]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries16]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=6
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries17]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries18]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=7
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries19]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries20]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=8
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries21]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries22]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=9
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries23]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries24]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=10
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries25]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries26]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=11
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries27]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries28]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=12
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries29]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries30]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=13
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries31]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries32]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=14
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.ext_entries]
-type=X86IntelMPBusHierarchy
-bus_id=0
-parent_bus=1
-subtractive_decode=true
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=true
-width=64
-default=system.pc.pciconfig.pio
-port=system.bridge.side_a system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma
-
-[system.iocache]
-type=BaseCache
-addr_range=0:134217727
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[18]
-mem_side=system.membus.port[2]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[3]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
-
-[system.membus.badaddr_responder]
-type=IsaFake
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.pc]
-type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal
-intrctrl=system.intrctrl
-system=system
-
-[system.pc.behind_pci]
-type=IsaFake
-pio_addr=9223372036854779128
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[12]
-
-[system.pc.com_1]
-type=Uart8250
-pio_addr=9223372036854776824
-pio_latency=1000
-platform=system.pc
-system=system
-terminal=system.pc.terminal
-pio=system.iobus.port[13]
-
-[system.pc.fake_com_2]
-type=IsaFake
-pio_addr=9223372036854776568
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[14]
-
-[system.pc.fake_com_3]
-type=IsaFake
-pio_addr=9223372036854776808
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[15]
-
-[system.pc.fake_com_4]
-type=IsaFake
-pio_addr=9223372036854776552
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[16]
-
-[system.pc.fake_floppy]
-type=IsaFake
-pio_addr=9223372036854776818
-pio_latency=1000
-pio_size=2
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[17]
-
-[system.pc.i_dont_exist]
-type=IsaFake
-pio_addr=9223372036854775936
-pio_latency=1000
-pio_size=1
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[11]
-
-[system.pc.pciconfig]
-type=PciConfigAll
-bus=0
-pio_latency=1
-platform=system.pc
-size=16777216
-system=system
-pio=system.iobus.default
-
-[system.pc.south_bridge]
-type=SouthBridge
-children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
-cmos=system.pc.south_bridge.cmos
-dma1=system.pc.south_bridge.dma1
-int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6
-io_apic=system.pc.south_bridge.io_apic
-keyboard=system.pc.south_bridge.keyboard
-pic1=system.pc.south_bridge.pic1
-pic2=system.pc.south_bridge.pic2
-pio_latency=1000
-pit=system.pc.south_bridge.pit
-platform=system.pc
-speaker=system.pc.south_bridge.speaker
-
-[system.pc.south_bridge.cmos]
-type=Cmos
-int_pin=system.pc.south_bridge.int_lines2.source
-pio_addr=9223372036854775920
-pio_latency=1000
-platform=system.pc
-system=system
-time=Sun Jan 1 00:00:00 2012
-pio=system.iobus.port[1]
-
-[system.pc.south_bridge.dma1]
-type=I8237
-pio_addr=9223372036854775808
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[2]
-
-[system.pc.south_bridge.ide]
-type=IdeController
-children=disks0 disks1
-BAR0=496
-BAR0LegacyIO=true
-BAR0Size=8
-BAR1=1012
-BAR1LegacyIO=true
-BAR1Size=3
-BAR2=368
-BAR2LegacyIO=true
-BAR2Size=8
-BAR3=884
-BAR3LegacyIO=true
-BAR3Size=3
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=14
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=128
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=0
-disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
-io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=4
-pci_func=0
-pio_latency=1000
-platform=system.pc
-system=system
-config=system.iobus.port[19]
-dma=system.iobus.port[20]
-pio=system.iobus.port[3]
-
-[system.pc.south_bridge.ide.disks0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks0.image
-
-[system.pc.south_bridge.ide.disks0.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
-read_only=true
-
-[system.pc.south_bridge.ide.disks1]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks1.image
-
-[system.pc.south_bridge.ide.disks1.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks1.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks1.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
-read_only=true
-
-[system.pc.south_bridge.int_lines0]
-type=X86IntLine
-children=sink source
-sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.int_lines0.source
-
-[system.pc.south_bridge.int_lines0.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=0
-
-[system.pc.south_bridge.int_lines0.source]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.int_lines1]
-type=X86IntLine
-children=sink source
-sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.int_lines1.source
-
-[system.pc.south_bridge.int_lines1.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=2
-
-[system.pc.south_bridge.int_lines1.source]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.int_lines2]
-type=X86IntLine
-children=sink source
-sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.int_lines2.source
-
-[system.pc.south_bridge.int_lines2.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic2
-number=0
-
-[system.pc.south_bridge.int_lines2.source]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.int_lines3]
-type=X86IntLine
-children=sink source
-sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.int_lines3.source
-
-[system.pc.south_bridge.int_lines3.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=0
-
-[system.pc.south_bridge.int_lines3.source]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.int_lines4]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.int_lines3.source
-
-[system.pc.south_bridge.int_lines4.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=2
-
-[system.pc.south_bridge.int_lines5]
-type=X86IntLine
-children=sink source
-sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.int_lines5.source
-
-[system.pc.south_bridge.int_lines5.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=1
-
-[system.pc.south_bridge.int_lines5.source]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.int_lines6]
-type=X86IntLine
-children=sink source
-sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.int_lines6.source
-
-[system.pc.south_bridge.int_lines6.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=12
-
-[system.pc.south_bridge.int_lines6.source]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.io_apic]
-type=I82094AA
-apic_id=1
-external_int_pic=system.pc.south_bridge.pic1
-int_latency=1000
-pio_addr=4273995776
-pio_latency=1000
-platform=system.pc
-system=system
-int_port=system.iobus.port[10]
-pio=system.iobus.port[9]
-
-[system.pc.south_bridge.keyboard]
-type=I8042
-command_port=9223372036854775908
-data_port=9223372036854775904
-keyboard_int_pin=system.pc.south_bridge.int_lines5.source
-mouse_int_pin=system.pc.south_bridge.int_lines6.source
-pio_addr=0
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[4]
-
-[system.pc.south_bridge.pic1]
-type=I8259
-mode=I8259Master
-output=system.pc.south_bridge.int_lines0.source
-pio_addr=9223372036854775840
-pio_latency=1000
-platform=system.pc
-slave=system.pc.south_bridge.pic2
-system=system
-pio=system.iobus.port[5]
-
-[system.pc.south_bridge.pic2]
-type=I8259
-mode=I8259Slave
-output=system.pc.south_bridge.int_lines1.source
-pio_addr=9223372036854775968
-pio_latency=1000
-platform=system.pc
-slave=Null
-system=system
-pio=system.iobus.port[6]
-
-[system.pc.south_bridge.pit]
-type=I8254
-int_pin=system.pc.south_bridge.int_lines3.source
-pio_addr=9223372036854775872
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[7]
-
-[system.pc.south_bridge.speaker]
-type=PcSpeaker
-i8254=system.pc.south_bridge.pit
-pio_addr=9223372036854775905
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[8]
-
-[system.pc.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
-[system.smbios_table]
-type=X86SMBiosSMBiosTable
-children=structures
-major_version=2
-minor_version=5
-structures=system.smbios_table.structures
-
-[system.smbios_table.structures]
-type=X86SMBiosBiosInformation
-characteristic_ext_bytes=
-characteristics=
-emb_cont_firmware_major=0
-emb_cont_firmware_minor=0
-major=0
-minor=0
-release_date=06/08/2008
-rom_size=0
-starting_addr_segment=0
-vendor=
-version=
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
-
+++ /dev/null
-warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
-warn: Reading current count from inactive timer.
-For more information see: http://www.m5sim.org/warn/1ea2be46
-warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Don't know what interrupt to clear for console.
-For more information see: http://www.m5sim.org/warn/7fe1004f
-warn: instruction 'fxsave' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
-warn: Tried to clear PCI interrupt 14
-For more information see: http://www.m5sim.org/warn/77378d57
-warn: Unknown mouse command 0xe1.
-For more information see: http://www.m5sim.org/warn/2447512a
-warn: instruction 'wbinvd' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
-hack: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Feb 26 2011 16:13:31
-M5 revision 412ef0f728a5 8092 default qtip tip updatefsstats.patch
-M5 started Feb 26 2011 16:13:35
-M5 executing on burrito
-command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
- 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5195470393000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1546136 # Simulator instruction rate (inst/s)
-host_mem_usage 364716 # Number of bytes of host memory used
-host_seconds 170.97 # Real time elapsed on the host
-host_tick_rate 30388572127 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 264339287 # Number of instructions simulated
-sim_seconds 5.195470 # Number of seconds simulated
-sim_ticks 5195470393000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses::0 13288006 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13288006 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15144.526649 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12144.494227 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0 11977182 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 11977182 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 19851809000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0 0.098647 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 1310824 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1310824 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 15919294500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098647 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1310824 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 75925324500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_accesses::0 8347353 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 8347353 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 30172.881044 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27172.847747 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0 8032009 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 8032009 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 9514837000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0 0.037778 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 315344 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 315344 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 8568794500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.037778 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 315344 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1379728500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 12.322779 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 21635359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 21635359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 18058.802043 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 15058.769451 # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 20009191 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 20009191 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 29366646000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.075163 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 1626168 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1626168 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 24488089000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0.075163 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1626168 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999995 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 511.997312 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses::0 21635359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 21635359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 18058.802043 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 15058.769451 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 20009191 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 20009191 # number of overall hits
-system.cpu.dcache.overall_miss_latency 29366646000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0 0.075163 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0 1626168 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 1626168 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 24488089000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0 0.075163 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1626168 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 77305053000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 1623424 # number of replacements
-system.cpu.dcache.sampled_refs 1623936 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use
-system.cpu.dcache.total_refs 20011404 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 44345000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 1529951 # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_accesses::1 21947 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 21947 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 11678.900629 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 8678.844424 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_hits::1 13051 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 13051 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_miss_latency 103895500 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.405340 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_misses::1 8896 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 8896 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 77207000 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.405340 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses 8896 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.avg_refs 1.691420 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::1 21947 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 21947 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 11678.900629 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 8678.844424 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::1 13051 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 13051 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_miss_latency 103895500 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::1 0.405340 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::1 8896 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 8896 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency 77207000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.405340 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_misses 8896 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
-system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.occ_%::1 0.315775 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_blocks::1 5.052403 # Average occupied blocks per context
-system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::1 21947 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 11678.900629 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 8678.844424 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::1 13051 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 13051 # number of overall hits
-system.cpu.dtb_walker_cache.overall_miss_latency 103895500 # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::1 0.405340 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::1 8896 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total 8896 # number of overall misses
-system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency 77207000 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.405340 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_misses 8896 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dtb_walker_cache.replacements 7704 # number of replacements
-system.cpu.dtb_walker_cache.sampled_refs 7716 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs 13051 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5160674969000 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.writebacks 2985 # number of writebacks
-system.cpu.icache.ReadReq_accesses::0 159222590 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 159222590 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 14812.203135 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11810.878733 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::0 158433932 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 158433932 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 11681762500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::0 0.004953 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0 788658 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 788658 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 9314744000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0 0.004953 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 788658 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 200.892324 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses::0 159222590 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 159222590 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 14812.203135 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11810.878733 # average overall mshr miss latency
-system.cpu.icache.demand_hits::0 158433932 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 158433932 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 11681762500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0 0.004953 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.demand_misses::0 788658 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 788658 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 9314744000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0 0.004953 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 788658 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.996799 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 510.361283 # Average occupied blocks per context
-system.cpu.icache.overall_accesses::0 159222590 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 159222590 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 14812.203135 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11810.878733 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 158433932 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 158433932 # number of overall hits
-system.cpu.icache.overall_miss_latency 11681762500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0 0.004953 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.overall_misses::0 788658 # number of overall misses
-system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 788658 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 9314744000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0 0.004953 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 788658 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 788139 # number of replacements
-system.cpu.icache.sampled_refs 788651 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 510.361283 # Cycle average of tags in use
-system.cpu.icache.total_refs 158433932 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 160047116000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 805 # number of writebacks
-system.cpu.idle_fraction 0.941953 # Percentage of idle cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::1 12221 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 11042.372881 # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 8042.372881 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_hits::1 7619 # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total 7619 # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_miss_latency 50817000 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.376565 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_misses::1 4602 # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total 4602 # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 37011000 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.376565 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses 4602 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.avg_refs 2.005046 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::1 12223 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::1 11042.372881 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 8042.372881 # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::1 7621 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total 7621 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_miss_latency 50817000 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::1 0.376503 # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::1 4602 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total 4602 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.itb_walker_cache.demand_mshr_miss_latency 37011000 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.376503 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_misses 4602 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
-system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.occ_%::1 0.191913 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.occ_blocks::1 3.070606 # Average occupied blocks per context
-system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::1 12223 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::1 11042.372881 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 8042.372881 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::1 7621 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total 7621 # number of overall hits
-system.cpu.itb_walker_cache.overall_miss_latency 50817000 # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::1 0.376503 # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::1 4602 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total 4602 # number of overall misses
-system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.itb_walker_cache.overall_mshr_miss_latency 37011000 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.376503 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_misses 4602 # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.itb_walker_cache.replacements 3754 # number of replacements
-system.cpu.itb_walker_cache.sampled_refs 3765 # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs 7549 # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5178573163000 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.writebacks 826 # number of writebacks
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.not_idle_fraction 0.058047 # Percentage of non-idle cycles
-system.cpu.numCycles 10390940786 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 603163545.121884 # Number of busy cycles
-system.cpu.num_conditional_control_insts 24882695 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_idle_cycles 9787777240.878117 # Number of idle cycles
-system.cpu.num_insts 264339287 # Number of instructions executed
-system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses
-system.cpu.num_int_insts 249556386 # number of integer instructions
-system.cpu.num_int_register_reads 543487907 # number of times the integer registers were read
-system.cpu.num_int_register_writes 266037487 # number of times the integer registers were written
-system.cpu.num_load_insts 14812525 # Number of load instructions
-system.cpu.num_mem_refs 23169904 # number of memory refs
-system.cpu.num_store_insts 8357379 # Number of store instructions
-system.iocache.ReadReq_accesses::1 844 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 126274.800948 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 74249.973934 # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency 106575932 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses::1 844 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 844 # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency 62666978 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_misses 844 # number of ReadReq MSHR misses
-system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 136801.779966 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 84796.168622 # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency 6391379160 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency 3961676998 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 47564 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 136614.983853 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 84609.031536 # average overall mshr miss latency
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 6497955092 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 47564 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47564 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 4024343976 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 47564 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.occ_%::1 0.007537 # Average percentage of cache occupancy
-system.iocache.occ_blocks::1 0.120586 # Average occupied blocks per context
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 47564 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 136614.983853 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 84609.031536 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.overall_miss_latency 6497955092 # number of overall miss cycles
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 47564 # number of overall misses
-system.iocache.overall_misses::total 47564 # number of overall misses
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 4024343976 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 47564 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.replacements 47510 # number of replacements
-system.iocache.sampled_refs 47526 # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0.120586 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 46668 # number of writebacks
-system.l2c.ReadExReq_accesses::0 313126 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 313126 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 52004.897310 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40004.868185 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0 192958 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 192958 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency 6249324500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0 0.383769 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 120168 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 120168 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 4807305000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0 0.383769 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 120168 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 2098689 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 9584 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2108273 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 52278.672230 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 115483586.956522 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 115535865.628752 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40254.652764 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0 2047882 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 9561 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2057443 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 2656122500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0 0.024209 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.002400 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.026609 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 50807 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 23 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 50830 # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency 2046144000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.024220 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 5.303631 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 5.327851 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 50830 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 56051785000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses::0 1689 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1689 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 24673.484295 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40254.930606 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0 320 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency 33778000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0 0.810539 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 1369 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 55109000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0 0.810539 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 1369 # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1218050000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0 1534567 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 1534567 # number of Writeback hits
-system.l2c.Writeback_hits::total 1534567 # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 19.991025 # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 2411815 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 9584 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2421399 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 52086.252376 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 387193347.826087 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 387245434.078463 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency
-system.l2c.demand_hits::0 2240840 # number of demand (read+write) hits
-system.l2c.demand_hits::1 9561 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 8905447000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.070891 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.002400 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.073290 # miss rate for demand accesses
-system.l2c.demand_misses::0 170975 # number of demand (read+write) misses
-system.l2c.demand_misses::1 23 # number of demand (read+write) misses
-system.l2c.demand_misses::total 170998 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 6853449000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.070900 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 17.842028 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 17.912929 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 170998 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.120711 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.358261 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 7910.895776 # Average occupied blocks per context
-system.l2c.occ_blocks::1 23478.999694 # Average occupied blocks per context
-system.l2c.overall_accesses::0 2411815 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 9584 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2421399 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 52086.252376 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 387193347.826087 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 387245434.078463 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 2240840 # number of overall hits
-system.l2c.overall_hits::1 9561 # number of overall hits
-system.l2c.overall_hits::total 2250401 # number of overall hits
-system.l2c.overall_miss_latency 8905447000 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.070891 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.002400 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.073290 # miss rate for overall accesses
-system.l2c.overall_misses::0 170975 # number of overall misses
-system.l2c.overall_misses::1 23 # number of overall misses
-system.l2c.overall_misses::total 170998 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 6853449000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.070900 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 17.842028 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 17.912929 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 170998 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 57269835000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 136133 # number of replacements
-system.l2c.sampled_refs 168244 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use
-system.l2c.total_refs 3363370 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 116255 # number of writebacks
-system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-
----------- End Simulation Statistics ----------
+++ /dev/null
-Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007\r
-Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
-BIOS-provided physical RAM map:\r
- BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)\r
- BIOS-e820: 0000000000100000 - 0000000008000000 (usable)\r
-end_pfn_map = 32768\r
-kernel direct mapping tables up to 8000000 @ 100000-102000\r
-DMI 2.5 present.\r
-Zone PFN ranges:\r
- DMA 256 -> 4096\r
- DMA32 4096 -> 1048576\r
- Normal 1048576 -> 1048576\r
-early_node_map[1] active PFN ranges\r
- 0: 256 -> 32768\r
-Intel MultiProcessor Specification v1.4\r
-MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000\r
-Processor #0 (Bootup-CPU)\r
-I/O APIC #1 at 0xFEC00000.\r
-Setting APIC routing to flat\r
-Processors: 1\r
-Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)\r
-Built 1 zonelists. Total pages: 30458\r
-Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
-Initializing CPU#0\r
-PID hash table entries: 512 (order: 9, 4096 bytes)\r
-time.c: Detected 1999.998 MHz processor.\r
-Console: colour dummy device 80x25\r
-console handover: boot [earlyser0] -> real [ttyS0]\r
-Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)\r
-Checking aperture...\r
-Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)\r
-Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
-Mount-cache hash table entries: 256\r
-CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
-CPU: L2 Cache: 1024K (64 bytes/line)\r
-CPU: Fake M5 x86_64 CPU stepping 01\r
-ACPI: Core revision 20070126\r
-ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]\r
-ACPI: Unable to load the System Description Tables\r
-Using local APIC timer interrupts.\r
-result 7812489\r
-Detected 7.812 MHz APIC timer.\r
-NET: Registered protocol family 16\r
-PCI: Using configuration type 1\r
-ACPI: Interpreter disabled.\r
-Linux Plug and Play Support v0.97 (c) Adam Belay\r
-pnp: PnP ACPI: disabled\r
-SCSI subsystem initialized\r
-usbcore: registered new interface driver usbfs\r
-usbcore: registered new interface driver hub\r
-usbcore: registered new device driver usb\r
-PCI: Probing PCI hardware\r
-PCI-GART: No AMD northbridge found.\r
-Time: tsc clocksource has been installed.\r
-NET: Registered protocol family 2\r
-IP route cache hash table entries: 1024 (order: 1, 8192 bytes)\r
-TCP established hash table entries: 4096 (order: 4, 65536 bytes)\r
-TCP bind hash table entries: 4096 (order: 3, 32768 bytes)\r
-TCP: Hash tables configured (established 4096 bind 4096)\r
-TCP reno registered\r
-Total HugeTLB memory allocated, 0\r
-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).\r
-io scheduler noop registered\r
-io scheduler deadline registered\r
-io scheduler cfq registered (default)\r
-Real Time Clock Driver v1.12ac\r
-Linux agpgart interface v0.102 (c) Dave Jones\r
-Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled\r
-serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250\r
-floppy0: no floppy controllers found\r
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize\r
-loop: module loaded\r
-Intel(R) PRO/1000 Network Driver - version 7.3.20-k2\r
-Copyright (c) 1999-2006 Intel Corporation.\r
-e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI\r
-e100: Copyright(c) 1999-2006 Intel Corporation\r
-forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.\r
-tun: Universal TUN/TAP device driver, 1.6\r
-tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>\r
-netconsole: not configured, aborting\r
-Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2\r
-ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx\r
-PIIX4: IDE controller at PCI slot 0000:00:04.0\r
-PCI: Enabling device 0000:00:04.0 (0000 -> 0001)\r
-PIIX4: chipset revision 0\r
-PIIX4: not 100% native mode: will probe irqs later\r
- ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA\r
- ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA\r
-hda: M5 IDE Disk, ATA DISK drive\r
-hdb: M5 IDE Disk, ATA DISK drive\r
-ide0 at 0x1f0-0x1f7,0x3f6 on irq 14\r
-hda: max request size: 128KiB\r
-hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)\r
- hda: hda1\r
-hdb: max request size: 128KiB\r
-hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)\r
- hdb: unknown partition table\r
-megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)\r
-megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)\r
-megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007\r
-Fusion MPT base driver 3.04.04\r
-Copyright (c) 1999-2007 LSI Logic Corporation\r
-Fusion MPT SPI Host driver 3.04.04\r
-Fusion MPT SAS Host driver 3.04.04\r
-ieee1394: raw1394: /dev/raw1394 device initialized\r
-USB Universal Host Controller Interface driver v3.0\r
-usbcore: registered new interface driver usblp\r
-drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver\r
-Initializing USB Mass Storage driver...\r
-usbcore: registered new interface driver usb-storage\r
-USB Mass Storage support registered.\r
-PNP: No PS/2 controller found. Probing ports directly.\r
-serio: i8042 KBD port at 0x60,0x64 irq 1\r
-serio: i8042 AUX port at 0x60,0x64 irq 12\r
-mice: PS/2 mouse device common for all mice\r
-input: AT Translated Set 2 keyboard as /class/input/input0\r
-device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com\r
-input: PS/2 Generic Mouse as /class/input/input1\r
-usbcore: registered new interface driver usbhid\r
-drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver\r
-oprofile: using timer interrupt.\r
-TCP cubic registered\r
-NET: Registered protocol family 1\r
-NET: Registered protocol family 10\r
-IPv6 over IPv4 tunneling driver\r
-NET: Registered protocol family 17\r
-EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended\r
-VFS: Mounted root (ext2 filesystem).\r
-Freeing unused kernel memory: 232k freed\r
-\rINIT: version 2.86 booting\r\r
-mounting filesystems...\r
-loading script...\r
--- /dev/null
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxX86System
+children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
+acpi_description_table_pointer=system.acpi_description_table_pointer
+boot_cpu_frequency=500
+boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+e820_table=system.e820_table
+init_param=0
+intel_mp_pointer=system.intel_mp_pointer
+intel_mp_table=system.intel_mp_table
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+load_addr_mask=18446744073709551615
+mem_mode=atomic
+physmem=system.physmem
+readfile=tests/halt.sh
+smbios_table=system.smbios_table
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+
+[system.acpi_description_table_pointer]
+type=X86ACPIRSDP
+children=xsdt
+oem_id=
+revision=2
+rsdt=Null
+xsdt=system.acpi_description_table_pointer.xsdt
+
+[system.acpi_description_table_pointer.xsdt]
+type=X86ACPIXSDT
+creator_id=
+creator_revision=0
+entries=
+oem_id=
+oem_revision=0
+oem_table_id=
+
+[system.bridge]
+type=Bridge
+delay=50000
+filter_ranges_a=0:1152921504606846975
+filter_ranges_b=0:134217727
+nack_delay=4000
+req_size_a=16
+req_size_b=16
+resp_size_a=16
+resp_size_b=16
+write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[1]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache tracer
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu.dtb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.dtb_walker_cache.cpu_side
+
+[system.cpu.dtb_walker_cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dtb.walker.port
+mem_side=system.toL2Bus.port[4]
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+platform=system.pc
+system=system
+int_port=system.membus.port[5]
+pio=system.membus.port[4]
+
+[system.cpu.itb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.itb_walker_cache.cpu_side
+
+[system.cpu.itb_walker_cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.itb.walker.port
+mem_side=system.toL2Bus.port[3]
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.e820_table]
+type=X86E820Table
+children=entries0 entries1
+entries=system.e820_table.entries0 system.e820_table.entries1
+
+[system.e820_table.entries0]
+type=X86E820Entry
+addr=0
+range_type=2
+size=1048576
+
+[system.e820_table.entries1]
+type=X86E820Entry
+addr=1048576
+range_type=1
+size=133169152
+
+[system.intel_mp_pointer]
+type=X86IntelMPFloatingPointer
+default_config=0
+imcr_present=true
+spec_rev=4
+
+[system.intel_mp_table]
+type=X86IntelMPConfigTable
+children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
+base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
+ext_entries=system.intel_mp_table.ext_entries
+local_apic=4276092928
+oem_id=
+oem_table_addr=0
+oem_table_size=0
+product_id=
+spec_rev=4
+
+[system.intel_mp_table.base_entries00]
+type=X86IntelMPProcessor
+bootstrap=true
+enable=true
+family=0
+feature_flags=0
+local_apic_id=0
+local_apic_version=20
+model=0
+stepping=0
+
+[system.intel_mp_table.base_entries01]
+type=X86IntelMPIOAPIC
+address=4273995776
+enable=true
+id=1
+version=17
+
+[system.intel_mp_table.base_entries02]
+type=X86IntelMPBus
+bus_id=0
+bus_type=ISA
+
+[system.intel_mp_table.base_entries03]
+type=X86IntelMPBus
+bus_id=1
+bus_type=PCI
+
+[system.intel_mp_table.base_entries04]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=16
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=1
+source_bus_irq=16
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries05]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=0
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries06]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=2
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=0
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries07]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=1
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries08]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=1
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=1
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries09]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=3
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries10]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=3
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=3
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries11]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=4
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries12]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=4
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=4
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries13]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=5
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries14]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=5
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=5
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries15]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=6
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries16]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=6
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=6
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries17]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=7
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries18]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=7
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=7
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries19]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=8
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries20]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=8
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=8
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries21]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=9
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries22]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=9
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=9
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries23]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=10
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries24]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=10
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=10
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries25]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=11
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries26]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=11
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=11
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries27]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=12
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries28]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=12
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=12
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries29]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=13
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries30]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=13
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=13
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries31]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=14
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries32]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=14
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=14
+trigger=ConformTrigger
+
+[system.intel_mp_table.ext_entries]
+type=X86IntelMPBusHierarchy
+bus_id=0
+parent_bus=1
+subtractive_decode=true
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=true
+width=64
+default=system.pc.pciconfig.pio
+port=system.bridge.side_a system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma
+
+[system.iocache]
+type=BaseCache
+addr_range=0:134217727
+assoc=8
+block_size=64
+forward_snoops=false
+hash_delay=1
+latency=50000
+max_miss_count=0
+mshrs=20
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[18]
+mem_side=system.membus.port[2]
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=10000
+max_miss_count=0
+mshrs=92
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=4194304
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[3]
+
+[system.membus]
+type=Bus
+children=badaddr_responder
+block_size=64
+bus_id=1
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+default=system.membus.badaddr_responder.pio
+port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+
+[system.membus.badaddr_responder]
+type=IsaFake
+pio_addr=0
+pio_latency=1000
+pio_size=8
+platform=system.pc
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.default
+
+[system.pc]
+type=Pc
+children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal
+intrctrl=system.intrctrl
+system=system
+
+[system.pc.behind_pci]
+type=IsaFake
+pio_addr=9223372036854779128
+pio_latency=1000
+pio_size=8
+platform=system.pc
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[12]
+
+[system.pc.com_1]
+type=Uart8250
+pio_addr=9223372036854776824
+pio_latency=1000
+platform=system.pc
+system=system
+terminal=system.pc.terminal
+pio=system.iobus.port[13]
+
+[system.pc.fake_com_2]
+type=IsaFake
+pio_addr=9223372036854776568
+pio_latency=1000
+pio_size=8
+platform=system.pc
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[14]
+
+[system.pc.fake_com_3]
+type=IsaFake
+pio_addr=9223372036854776808
+pio_latency=1000
+pio_size=8
+platform=system.pc
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[15]
+
+[system.pc.fake_com_4]
+type=IsaFake
+pio_addr=9223372036854776552
+pio_latency=1000
+pio_size=8
+platform=system.pc
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[16]
+
+[system.pc.fake_floppy]
+type=IsaFake
+pio_addr=9223372036854776818
+pio_latency=1000
+pio_size=2
+platform=system.pc
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[17]
+
+[system.pc.i_dont_exist]
+type=IsaFake
+pio_addr=9223372036854775936
+pio_latency=1000
+pio_size=1
+platform=system.pc
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[11]
+
+[system.pc.pciconfig]
+type=PciConfigAll
+bus=0
+pio_latency=1
+platform=system.pc
+size=16777216
+system=system
+pio=system.iobus.default
+
+[system.pc.south_bridge]
+type=SouthBridge
+children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
+cmos=system.pc.south_bridge.cmos
+dma1=system.pc.south_bridge.dma1
+int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6
+io_apic=system.pc.south_bridge.io_apic
+keyboard=system.pc.south_bridge.keyboard
+pic1=system.pc.south_bridge.pic1
+pic2=system.pc.south_bridge.pic2
+pio_latency=1000
+pit=system.pc.south_bridge.pit
+platform=system.pc
+speaker=system.pc.south_bridge.speaker
+
+[system.pc.south_bridge.cmos]
+type=Cmos
+int_pin=system.pc.south_bridge.int_lines2.source
+pio_addr=9223372036854775920
+pio_latency=1000
+platform=system.pc
+system=system
+time=Sun Jan 1 00:00:00 2012
+pio=system.iobus.port[1]
+
+[system.pc.south_bridge.dma1]
+type=I8237
+pio_addr=9223372036854775808
+pio_latency=1000
+platform=system.pc
+system=system
+pio=system.iobus.port[2]
+
+[system.pc.south_bridge.ide]
+type=IdeController
+children=disks0 disks1
+BAR0=496
+BAR0LegacyIO=true
+BAR0Size=8
+BAR1=1012
+BAR1LegacyIO=true
+BAR1Size=3
+BAR2=368
+BAR2LegacyIO=true
+BAR2Size=8
+BAR3=884
+BAR3LegacyIO=true
+BAR3Size=3
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=14
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=128
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+config_latency=20000
+ctrl_offset=0
+disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
+io_shift=0
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=4
+pci_func=0
+pio_latency=1000
+platform=system.pc
+system=system
+config=system.iobus.port[19]
+dma=system.iobus.port[20]
+pio=system.iobus.port[3]
+
+[system.pc.south_bridge.ide.disks0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.pc.south_bridge.ide.disks0.image
+
+[system.pc.south_bridge.ide.disks0.image]
+type=CowDiskImage
+children=child
+child=system.pc.south_bridge.ide.disks0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.pc.south_bridge.ide.disks0.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-x86.img
+read_only=true
+
+[system.pc.south_bridge.ide.disks1]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.pc.south_bridge.ide.disks1.image
+
+[system.pc.south_bridge.ide.disks1.image]
+type=CowDiskImage
+children=child
+child=system.pc.south_bridge.ide.disks1.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.pc.south_bridge.ide.disks1.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-bigswap2.img
+read_only=true
+
+[system.pc.south_bridge.int_lines0]
+type=X86IntLine
+children=sink source
+sink=system.pc.south_bridge.int_lines0.sink
+source=system.pc.south_bridge.int_lines0.source
+
+[system.pc.south_bridge.int_lines0.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=0
+
+[system.pc.south_bridge.int_lines0.source]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.int_lines1]
+type=X86IntLine
+children=sink source
+sink=system.pc.south_bridge.int_lines1.sink
+source=system.pc.south_bridge.int_lines1.source
+
+[system.pc.south_bridge.int_lines1.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.pic1
+number=2
+
+[system.pc.south_bridge.int_lines1.source]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.int_lines2]
+type=X86IntLine
+children=sink source
+sink=system.pc.south_bridge.int_lines2.sink
+source=system.pc.south_bridge.int_lines2.source
+
+[system.pc.south_bridge.int_lines2.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.pic2
+number=0
+
+[system.pc.south_bridge.int_lines2.source]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.int_lines3]
+type=X86IntLine
+children=sink source
+sink=system.pc.south_bridge.int_lines3.sink
+source=system.pc.south_bridge.int_lines3.source
+
+[system.pc.south_bridge.int_lines3.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.pic1
+number=0
+
+[system.pc.south_bridge.int_lines3.source]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.int_lines4]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines4.sink
+source=system.pc.south_bridge.int_lines3.source
+
+[system.pc.south_bridge.int_lines4.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=2
+
+[system.pc.south_bridge.int_lines5]
+type=X86IntLine
+children=sink source
+sink=system.pc.south_bridge.int_lines5.sink
+source=system.pc.south_bridge.int_lines5.source
+
+[system.pc.south_bridge.int_lines5.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=1
+
+[system.pc.south_bridge.int_lines5.source]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.int_lines6]
+type=X86IntLine
+children=sink source
+sink=system.pc.south_bridge.int_lines6.sink
+source=system.pc.south_bridge.int_lines6.source
+
+[system.pc.south_bridge.int_lines6.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=12
+
+[system.pc.south_bridge.int_lines6.source]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.io_apic]
+type=I82094AA
+apic_id=1
+external_int_pic=system.pc.south_bridge.pic1
+int_latency=1000
+pio_addr=4273995776
+pio_latency=1000
+platform=system.pc
+system=system
+int_port=system.iobus.port[10]
+pio=system.iobus.port[9]
+
+[system.pc.south_bridge.keyboard]
+type=I8042
+command_port=9223372036854775908
+data_port=9223372036854775904
+keyboard_int_pin=system.pc.south_bridge.int_lines5.source
+mouse_int_pin=system.pc.south_bridge.int_lines6.source
+pio_addr=0
+pio_latency=1000
+platform=system.pc
+system=system
+pio=system.iobus.port[4]
+
+[system.pc.south_bridge.pic1]
+type=I8259
+mode=I8259Master
+output=system.pc.south_bridge.int_lines0.source
+pio_addr=9223372036854775840
+pio_latency=1000
+platform=system.pc
+slave=system.pc.south_bridge.pic2
+system=system
+pio=system.iobus.port[5]
+
+[system.pc.south_bridge.pic2]
+type=I8259
+mode=I8259Slave
+output=system.pc.south_bridge.int_lines1.source
+pio_addr=9223372036854775968
+pio_latency=1000
+platform=system.pc
+slave=Null
+system=system
+pio=system.iobus.port[6]
+
+[system.pc.south_bridge.pit]
+type=I8254
+int_pin=system.pc.south_bridge.int_lines3.source
+pio_addr=9223372036854775872
+pio_latency=1000
+platform=system.pc
+system=system
+pio=system.iobus.port[7]
+
+[system.pc.south_bridge.speaker]
+type=PcSpeaker
+i8254=system.pc.south_bridge.pit
+pio_addr=9223372036854775905
+pio_latency=1000
+platform=system.pc
+system=system
+pio=system.iobus.port[8]
+
+[system.pc.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
+[system.smbios_table]
+type=X86SMBiosSMBiosTable
+children=structures
+major_version=2
+minor_version=5
+structures=system.smbios_table.structures
+
+[system.smbios_table.structures]
+type=X86SMBiosBiosInformation
+characteristic_ext_bytes=
+characteristics=
+emb_cont_firmware_major=0
+emb_cont_firmware_minor=0
+major=0
+minor=0
+release_date=06/08/2008
+rom_size=0
+starting_addr_segment=0
+vendor=
+version=
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
+
--- /dev/null
+warn: Sockets disabled, not accepting terminal connections
+For more information see: http://www.m5sim.org/warn/8742226b
+warn: Reading current count from inactive timer.
+For more information see: http://www.m5sim.org/warn/1ea2be46
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Don't know what interrupt to clear for console.
+For more information see: http://www.m5sim.org/warn/7fe1004f
+warn: instruction 'fxsave' unimplemented
+For more information see: http://www.m5sim.org/warn/437d5238
+warn: Tried to clear PCI interrupt 14
+For more information see: http://www.m5sim.org/warn/77378d57
+warn: Unknown mouse command 0xe1.
+For more information see: http://www.m5sim.org/warn/2447512a
+warn: instruction 'wbinvd' unimplemented
+For more information see: http://www.m5sim.org/warn/437d5238
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Feb 26 2011 16:13:31
+M5 revision 412ef0f728a5 8092 default qtip tip updatefsstats.patch
+M5 started Feb 26 2011 16:13:35
+M5 executing on burrito
+command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+ 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 5112051446000 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2446370 # Simulator instruction rate (inst/s)
+host_mem_usage 368136 # Number of bytes of host memory used
+host_seconds 166.22 # Real time elapsed on the host
+host_tick_rate 30755543746 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 406624458 # Number of instructions simulated
+sim_seconds 5.112051 # Number of seconds simulated
+sim_ticks 5112051446000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses::0 13367989 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13367989 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits::0 12059464 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 12059464 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_rate::0 0.097885 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 1308525 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1308525 # number of ReadReq misses
+system.cpu.dcache.WriteReq_accesses::0 8403116 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 8403116 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_hits::0 8086815 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 8086815 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_rate::0 0.037641 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 316301 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 316301 # number of WriteReq misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 12.417813 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.itb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::1 7613 # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total 7613 # number of overall hits
+system.cpu.itb_walker_cache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::1 0.376954 # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::1 4606 # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total 4606 # number of overall misses
+system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.itb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.itb_walker_cache.replacements 3761 # number of replacements
+system.cpu.itb_walker_cache.sampled_refs 3771 # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.itb_walker_cache.tagsinuse 3.020778 # Cycle average of tags in use
+system.cpu.itb_walker_cache.total_refs 7582 # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.warmup_cycle 5105305893500 # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.writebacks 603 # number of writebacks
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
+system.cpu.numCycles 10224102915 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 453482144.002058 # Number of busy cycles
+system.cpu.num_conditional_control_insts 42460207 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu.num_fp_insts 0 # number of float instructions
+system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_idle_cycles 9770620770.997942 # Number of idle cycles
+system.cpu.num_insts 406624458 # Number of instructions executed
+system.cpu.num_int_alu_accesses 391833838 # Number of integer alu accesses
+system.cpu.num_int_insts 391833838 # number of integer instructions
+system.cpu.num_int_register_reads 836347889 # number of times the integer registers were read
+system.cpu.num_int_register_writes 419160873 # number of times the integer registers were written
+system.cpu.num_load_insts 29720540 # Number of load instructions
+system.cpu.num_mem_refs 38133606 # number of memory refs
+system.cpu.num_store_insts 8413066 # Number of store instructions
+system.iocache.ReadReq_accesses::1 909 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses::1 909 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
+system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
+system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.iocache.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
+system.iocache.demand_accesses::1 47629 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.demand_hits::0 0 # number of demand (read+write) hits
+system.iocache.demand_hits::1 0 # number of demand (read+write) hits
+system.iocache.demand_hits::total 0 # number of demand (read+write) hits
+system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
+system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
+system.iocache.demand_misses::0 0 # number of demand (read+write) misses
+system.iocache.demand_misses::1 47629 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47629 # number of demand (read+write) misses
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.occ_%::1 0.002653 # Average percentage of cache occupancy
+system.iocache.occ_blocks::1 0.042448 # Average occupied blocks per context
+system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
+system.iocache.overall_accesses::1 47629 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.iocache.overall_hits::0 0 # number of overall hits
+system.iocache.overall_hits::1 0 # number of overall hits
+system.iocache.overall_hits::total 0 # number of overall hits
+system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
+system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
+system.iocache.overall_misses::0 0 # number of overall misses
+system.iocache.overall_misses::1 47629 # number of overall misses
+system.iocache.overall_misses::total 47629 # number of overall misses
+system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.replacements 47574 # number of replacements
+system.iocache.sampled_refs 47590 # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse 0.042448 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.warmup_cycle 4994772176509 # Cycle when the warmup percentage was hit.
+system.iocache.writebacks 46667 # number of writebacks
+system.l2c.ReadExReq_accesses::0 314040 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 314040 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_hits::0 169169 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 169169 # number of ReadExReq hits
+system.l2c.ReadExReq_miss_rate::0 0.461314 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0 144871 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 144871 # number of ReadExReq misses
+system.l2c.ReadReq_accesses::0 2100261 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 10262 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2110523 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits::0 2044272 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 10235 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 2054507 # number of ReadReq hits
+system.l2c.ReadReq_miss_rate::0 0.026658 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.002631 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.029289 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0 55989 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 27 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 56016 # number of ReadReq misses
+system.l2c.UpgradeReq_accesses::0 1821 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 1821 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_hits::0 24 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_rate::0 0.986820 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 1797 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 1797 # number of UpgradeReq misses
+system.l2c.Writeback_accesses::0 1530354 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 1530354 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 1530354 # number of Writeback hits
+system.l2c.Writeback_hits::total 1530354 # number of Writeback hits
+system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.avg_refs 16.953097 # Average number of references to valid blocks.
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.demand_accesses::0 2414301 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 10262 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2424563 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.l2c.demand_hits::0 2213441 # number of demand (read+write) hits
+system.l2c.demand_hits::1 10235 # number of demand (read+write) hits
+system.l2c.demand_hits::total 2223676 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0 0.083196 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.002631 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.085827 # miss rate for demand accesses
+system.l2c.demand_misses::0 200860 # number of demand (read+write) misses
+system.l2c.demand_misses::1 27 # number of demand (read+write) misses
+system.l2c.demand_misses::total 200887 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.occ_%::0 0.147971 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.414180 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 9697.448079 # Average occupied blocks per context
+system.l2c.occ_blocks::1 27143.733047 # Average occupied blocks per context
+system.l2c.overall_accesses::0 2414301 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 10262 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2424563 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.l2c.overall_hits::0 2213441 # number of overall hits
+system.l2c.overall_hits::1 10235 # number of overall hits
+system.l2c.overall_hits::total 2223676 # number of overall hits
+system.l2c.overall_miss_latency 0 # number of overall miss cycles
+system.l2c.overall_miss_rate::0 0.083196 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.002631 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.085827 # miss rate for overall accesses
+system.l2c.overall_misses::0 200860 # number of overall misses
+system.l2c.overall_misses::1 27 # number of overall misses
+system.l2c.overall_misses::total 200887 # number of overall misses
+system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.replacements 164351 # number of replacements
+system.l2c.sampled_refs 196384 # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse 36841.181126 # Cycle average of tags in use
+system.l2c.total_refs 3329317 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 144194 # number of writebacks
+system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
+system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
+
+---------- End Simulation Statistics ----------
--- /dev/null
+Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007\r
+Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
+BIOS-provided physical RAM map:\r
+ BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)\r
+ BIOS-e820: 0000000000100000 - 0000000008000000 (usable)\r
+end_pfn_map = 32768\r
+kernel direct mapping tables up to 8000000 @ 100000-102000\r
+DMI 2.5 present.\r
+Zone PFN ranges:\r
+ DMA 256 -> 4096\r
+ DMA32 4096 -> 1048576\r
+ Normal 1048576 -> 1048576\r
+early_node_map[1] active PFN ranges\r
+ 0: 256 -> 32768\r
+Intel MultiProcessor Specification v1.4\r
+MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000\r
+Processor #0 (Bootup-CPU)\r
+I/O APIC #1 at 0xFEC00000.\r
+Setting APIC routing to flat\r
+Processors: 1\r
+Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)\r
+Built 1 zonelists. Total pages: 30458\r
+Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
+Initializing CPU#0\r
+PID hash table entries: 512 (order: 9, 4096 bytes)\r
+time.c: Detected 1999.998 MHz processor.\r
+Console: colour dummy device 80x25\r
+console handover: boot [earlyser0] -> real [ttyS0]\r
+Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
+Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)\r
+Checking aperture...\r
+Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)\r
+Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
+Mount-cache hash table entries: 256\r
+CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
+CPU: L2 Cache: 1024K (64 bytes/line)\r
+CPU: Fake M5 x86_64 CPU stepping 01\r
+ACPI: Core revision 20070126\r
+ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]\r
+ACPI: Unable to load the System Description Tables\r
+Using local APIC timer interrupts.\r
+result 7812490\r
+Detected 7.812 MHz APIC timer.\r
+NET: Registered protocol family 16\r
+PCI: Using configuration type 1\r
+ACPI: Interpreter disabled.\r
+Linux Plug and Play Support v0.97 (c) Adam Belay\r
+pnp: PnP ACPI: disabled\r
+SCSI subsystem initialized\r
+usbcore: registered new interface driver usbfs\r
+usbcore: registered new interface driver hub\r
+usbcore: registered new device driver usb\r
+PCI: Probing PCI hardware\r
+PCI-GART: No AMD northbridge found.\r
+NET: Registered protocol family 2\r
+Time: tsc clocksource has been installed.\r
+IP route cache hash table entries: 1024 (order: 1, 8192 bytes)\r
+TCP established hash table entries: 4096 (order: 4, 65536 bytes)\r
+TCP bind hash table entries: 4096 (order: 3, 32768 bytes)\r
+TCP: Hash tables configured (established 4096 bind 4096)\r
+TCP reno registered\r
+Total HugeTLB memory allocated, 0\r
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).\r
+io scheduler noop registered\r
+io scheduler deadline registered\r
+io scheduler cfq registered (default)\r
+Real Time Clock Driver v1.12ac\r
+Linux agpgart interface v0.102 (c) Dave Jones\r
+Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled\r
+serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250\r
+floppy0: no floppy controllers found\r
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize\r
+loop: module loaded\r
+Intel(R) PRO/1000 Network Driver - version 7.3.20-k2\r
+Copyright (c) 1999-2006 Intel Corporation.\r
+e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI\r
+e100: Copyright(c) 1999-2006 Intel Corporation\r
+forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.\r
+tun: Universal TUN/TAP device driver, 1.6\r
+tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>\r
+netconsole: not configured, aborting\r
+Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2\r
+ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx\r
+PIIX4: IDE controller at PCI slot 0000:00:04.0\r
+PCI: Enabling device 0000:00:04.0 (0000 -> 0001)\r
+PIIX4: chipset revision 0\r
+PIIX4: not 100% native mode: will probe irqs later\r
+ ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA\r
+ ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA\r
+hda: M5 IDE Disk, ATA DISK drive\r
+hdb: M5 IDE Disk, ATA DISK drive\r
+ide0 at 0x1f0-0x1f7,0x3f6 on irq 14\r
+hda: max request size: 128KiB\r
+hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)\r
+ hda: hda1\r
+hdb: max request size: 128KiB\r
+hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)\r
+ hdb: unknown partition table\r
+megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)\r
+megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)\r
+megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007\r
+Fusion MPT base driver 3.04.04\r
+Copyright (c) 1999-2007 LSI Logic Corporation\r
+Fusion MPT SPI Host driver 3.04.04\r
+Fusion MPT SAS Host driver 3.04.04\r
+ieee1394: raw1394: /dev/raw1394 device initialized\r
+USB Universal Host Controller Interface driver v3.0\r
+usbcore: registered new interface driver usblp\r
+drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver\r
+Initializing USB Mass Storage driver...\r
+usbcore: registered new interface driver usb-storage\r
+USB Mass Storage support registered.\r
+PNP: No PS/2 controller found. Probing ports directly.\r
+serio: i8042 KBD port at 0x60,0x64 irq 1\r
+serio: i8042 AUX port at 0x60,0x64 irq 12\r
+mice: PS/2 mouse device common for all mice\r
+input: AT Translated Set 2 keyboard as /class/input/input0\r
+device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com\r
+input: PS/2 Generic Mouse as /class/input/input1\r
+usbcore: registered new interface driver usbhid\r
+drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver\r
+oprofile: using timer interrupt.\r
+TCP cubic registered\r
+NET: Registered protocol family 1\r
+NET: Registered protocol family 10\r
+IPv6 over IPv4 tunneling driver\r
+NET: Registered protocol family 17\r
+EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended\r
+VFS: Mounted root (ext2 filesystem).\r
+Freeing unused kernel memory: 232k freed\r
+\rINIT: version 2.86 booting\r\r
+mounting filesystems...\r
+loading script...\r
--- /dev/null
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxX86System
+children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
+acpi_description_table_pointer=system.acpi_description_table_pointer
+boot_cpu_frequency=500
+boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+e820_table=system.e820_table
+init_param=0
+intel_mp_pointer=system.intel_mp_pointer
+intel_mp_table=system.intel_mp_table
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+load_addr_mask=18446744073709551615
+mem_mode=timing
+physmem=system.physmem
+readfile=tests/halt.sh
+smbios_table=system.smbios_table
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+
+[system.acpi_description_table_pointer]
+type=X86ACPIRSDP
+children=xsdt
+oem_id=
+revision=2
+rsdt=Null
+xsdt=system.acpi_description_table_pointer.xsdt
+
+[system.acpi_description_table_pointer.xsdt]
+type=X86ACPIXSDT
+creator_id=
+creator_revision=0
+entries=
+oem_id=
+oem_revision=0
+oem_table_id=
+
+[system.bridge]
+type=Bridge
+delay=50000
+filter_ranges_a=0:1152921504606846975
+filter_ranges_b=0:134217727
+nack_delay=4000
+req_size_a=16
+req_size_b=16
+resp_size_a=16
+resp_size_b=16
+write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[1]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache tracer
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu.dtb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.dtb_walker_cache.cpu_side
+
+[system.cpu.dtb_walker_cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dtb.walker.port
+mem_side=system.toL2Bus.port[4]
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=4
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+platform=system.pc
+system=system
+int_port=system.membus.port[5]
+pio=system.membus.port[4]
+
+[system.cpu.itb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.itb_walker_cache.cpu_side
+
+[system.cpu.itb_walker_cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.itb.walker.port
+mem_side=system.toL2Bus.port[3]
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.e820_table]
+type=X86E820Table
+children=entries0 entries1
+entries=system.e820_table.entries0 system.e820_table.entries1
+
+[system.e820_table.entries0]
+type=X86E820Entry
+addr=0
+range_type=2
+size=1048576
+
+[system.e820_table.entries1]
+type=X86E820Entry
+addr=1048576
+range_type=1
+size=133169152
+
+[system.intel_mp_pointer]
+type=X86IntelMPFloatingPointer
+default_config=0
+imcr_present=true
+spec_rev=4
+
+[system.intel_mp_table]
+type=X86IntelMPConfigTable
+children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
+base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
+ext_entries=system.intel_mp_table.ext_entries
+local_apic=4276092928
+oem_id=
+oem_table_addr=0
+oem_table_size=0
+product_id=
+spec_rev=4
+
+[system.intel_mp_table.base_entries00]
+type=X86IntelMPProcessor
+bootstrap=true
+enable=true
+family=0
+feature_flags=0
+local_apic_id=0
+local_apic_version=20
+model=0
+stepping=0
+
+[system.intel_mp_table.base_entries01]
+type=X86IntelMPIOAPIC
+address=4273995776
+enable=true
+id=1
+version=17
+
+[system.intel_mp_table.base_entries02]
+type=X86IntelMPBus
+bus_id=0
+bus_type=ISA
+
+[system.intel_mp_table.base_entries03]
+type=X86IntelMPBus
+bus_id=1
+bus_type=PCI
+
+[system.intel_mp_table.base_entries04]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=16
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=1
+source_bus_irq=16
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries05]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=0
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries06]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=2
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=0
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries07]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=1
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries08]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=1
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=1
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries09]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=3
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries10]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=3
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=3
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries11]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=4
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries12]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=4
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=4
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries13]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=5
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries14]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=5
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=5
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries15]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=6
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries16]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=6
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=6
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries17]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=7
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries18]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=7
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=7
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries19]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=8
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries20]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=8
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=8
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries21]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=9
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries22]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=9
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=9
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries23]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=10
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries24]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=10
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=10
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries25]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=11
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries26]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=11
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=11
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries27]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=12
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries28]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=12
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=12
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries29]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=13
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries30]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=13
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=13
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries31]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=14
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries32]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=1
+dest_io_apic_intin=14
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=14
+trigger=ConformTrigger
+
+[system.intel_mp_table.ext_entries]
+type=X86IntelMPBusHierarchy
+bus_id=0
+parent_bus=1
+subtractive_decode=true
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.iobus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=true
+width=64
+default=system.pc.pciconfig.pio
+port=system.bridge.side_a system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma
+
+[system.iocache]
+type=BaseCache
+addr_range=0:134217727
+assoc=8
+block_size=64
+forward_snoops=false
+hash_delay=1
+latency=50000
+max_miss_count=0
+mshrs=20
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[18]
+mem_side=system.membus.port[2]
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=10000
+max_miss_count=0
+mshrs=92
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=4194304
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[3]
+
+[system.membus]
+type=Bus
+children=badaddr_responder
+block_size=64
+bus_id=1
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+default=system.membus.badaddr_responder.pio
+port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+
+[system.membus.badaddr_responder]
+type=IsaFake
+pio_addr=0
+pio_latency=1000
+pio_size=8
+platform=system.pc
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.membus.default
+
+[system.pc]
+type=Pc
+children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal
+intrctrl=system.intrctrl
+system=system
+
+[system.pc.behind_pci]
+type=IsaFake
+pio_addr=9223372036854779128
+pio_latency=1000
+pio_size=8
+platform=system.pc
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[12]
+
+[system.pc.com_1]
+type=Uart8250
+pio_addr=9223372036854776824
+pio_latency=1000
+platform=system.pc
+system=system
+terminal=system.pc.terminal
+pio=system.iobus.port[13]
+
+[system.pc.fake_com_2]
+type=IsaFake
+pio_addr=9223372036854776568
+pio_latency=1000
+pio_size=8
+platform=system.pc
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[14]
+
+[system.pc.fake_com_3]
+type=IsaFake
+pio_addr=9223372036854776808
+pio_latency=1000
+pio_size=8
+platform=system.pc
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[15]
+
+[system.pc.fake_com_4]
+type=IsaFake
+pio_addr=9223372036854776552
+pio_latency=1000
+pio_size=8
+platform=system.pc
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[16]
+
+[system.pc.fake_floppy]
+type=IsaFake
+pio_addr=9223372036854776818
+pio_latency=1000
+pio_size=2
+platform=system.pc
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[17]
+
+[system.pc.i_dont_exist]
+type=IsaFake
+pio_addr=9223372036854775936
+pio_latency=1000
+pio_size=1
+platform=system.pc
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.port[11]
+
+[system.pc.pciconfig]
+type=PciConfigAll
+bus=0
+pio_latency=1
+platform=system.pc
+size=16777216
+system=system
+pio=system.iobus.default
+
+[system.pc.south_bridge]
+type=SouthBridge
+children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
+cmos=system.pc.south_bridge.cmos
+dma1=system.pc.south_bridge.dma1
+int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6
+io_apic=system.pc.south_bridge.io_apic
+keyboard=system.pc.south_bridge.keyboard
+pic1=system.pc.south_bridge.pic1
+pic2=system.pc.south_bridge.pic2
+pio_latency=1000
+pit=system.pc.south_bridge.pit
+platform=system.pc
+speaker=system.pc.south_bridge.speaker
+
+[system.pc.south_bridge.cmos]
+type=Cmos
+int_pin=system.pc.south_bridge.int_lines2.source
+pio_addr=9223372036854775920
+pio_latency=1000
+platform=system.pc
+system=system
+time=Sun Jan 1 00:00:00 2012
+pio=system.iobus.port[1]
+
+[system.pc.south_bridge.dma1]
+type=I8237
+pio_addr=9223372036854775808
+pio_latency=1000
+platform=system.pc
+system=system
+pio=system.iobus.port[2]
+
+[system.pc.south_bridge.ide]
+type=IdeController
+children=disks0 disks1
+BAR0=496
+BAR0LegacyIO=true
+BAR0Size=8
+BAR1=1012
+BAR1LegacyIO=true
+BAR1Size=3
+BAR2=368
+BAR2LegacyIO=true
+BAR2Size=8
+BAR3=884
+BAR3LegacyIO=true
+BAR3Size=3
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=14
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=128
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+config_latency=20000
+ctrl_offset=0
+disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
+io_shift=0
+max_backoff_delay=10000000
+min_backoff_delay=4000
+pci_bus=0
+pci_dev=4
+pci_func=0
+pio_latency=1000
+platform=system.pc
+system=system
+config=system.iobus.port[19]
+dma=system.iobus.port[20]
+pio=system.iobus.port[3]
+
+[system.pc.south_bridge.ide.disks0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.pc.south_bridge.ide.disks0.image
+
+[system.pc.south_bridge.ide.disks0.image]
+type=CowDiskImage
+children=child
+child=system.pc.south_bridge.ide.disks0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.pc.south_bridge.ide.disks0.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-x86.img
+read_only=true
+
+[system.pc.south_bridge.ide.disks1]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.pc.south_bridge.ide.disks1.image
+
+[system.pc.south_bridge.ide.disks1.image]
+type=CowDiskImage
+children=child
+child=system.pc.south_bridge.ide.disks1.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.pc.south_bridge.ide.disks1.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-bigswap2.img
+read_only=true
+
+[system.pc.south_bridge.int_lines0]
+type=X86IntLine
+children=sink source
+sink=system.pc.south_bridge.int_lines0.sink
+source=system.pc.south_bridge.int_lines0.source
+
+[system.pc.south_bridge.int_lines0.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=0
+
+[system.pc.south_bridge.int_lines0.source]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.int_lines1]
+type=X86IntLine
+children=sink source
+sink=system.pc.south_bridge.int_lines1.sink
+source=system.pc.south_bridge.int_lines1.source
+
+[system.pc.south_bridge.int_lines1.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.pic1
+number=2
+
+[system.pc.south_bridge.int_lines1.source]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.int_lines2]
+type=X86IntLine
+children=sink source
+sink=system.pc.south_bridge.int_lines2.sink
+source=system.pc.south_bridge.int_lines2.source
+
+[system.pc.south_bridge.int_lines2.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.pic2
+number=0
+
+[system.pc.south_bridge.int_lines2.source]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.int_lines3]
+type=X86IntLine
+children=sink source
+sink=system.pc.south_bridge.int_lines3.sink
+source=system.pc.south_bridge.int_lines3.source
+
+[system.pc.south_bridge.int_lines3.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.pic1
+number=0
+
+[system.pc.south_bridge.int_lines3.source]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.int_lines4]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines4.sink
+source=system.pc.south_bridge.int_lines3.source
+
+[system.pc.south_bridge.int_lines4.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=2
+
+[system.pc.south_bridge.int_lines5]
+type=X86IntLine
+children=sink source
+sink=system.pc.south_bridge.int_lines5.sink
+source=system.pc.south_bridge.int_lines5.source
+
+[system.pc.south_bridge.int_lines5.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=1
+
+[system.pc.south_bridge.int_lines5.source]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.int_lines6]
+type=X86IntLine
+children=sink source
+sink=system.pc.south_bridge.int_lines6.sink
+source=system.pc.south_bridge.int_lines6.source
+
+[system.pc.south_bridge.int_lines6.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=12
+
+[system.pc.south_bridge.int_lines6.source]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.io_apic]
+type=I82094AA
+apic_id=1
+external_int_pic=system.pc.south_bridge.pic1
+int_latency=1000
+pio_addr=4273995776
+pio_latency=1000
+platform=system.pc
+system=system
+int_port=system.iobus.port[10]
+pio=system.iobus.port[9]
+
+[system.pc.south_bridge.keyboard]
+type=I8042
+command_port=9223372036854775908
+data_port=9223372036854775904
+keyboard_int_pin=system.pc.south_bridge.int_lines5.source
+mouse_int_pin=system.pc.south_bridge.int_lines6.source
+pio_addr=0
+pio_latency=1000
+platform=system.pc
+system=system
+pio=system.iobus.port[4]
+
+[system.pc.south_bridge.pic1]
+type=I8259
+mode=I8259Master
+output=system.pc.south_bridge.int_lines0.source
+pio_addr=9223372036854775840
+pio_latency=1000
+platform=system.pc
+slave=system.pc.south_bridge.pic2
+system=system
+pio=system.iobus.port[5]
+
+[system.pc.south_bridge.pic2]
+type=I8259
+mode=I8259Slave
+output=system.pc.south_bridge.int_lines1.source
+pio_addr=9223372036854775968
+pio_latency=1000
+platform=system.pc
+slave=Null
+system=system
+pio=system.iobus.port[6]
+
+[system.pc.south_bridge.pit]
+type=I8254
+int_pin=system.pc.south_bridge.int_lines3.source
+pio_addr=9223372036854775872
+pio_latency=1000
+platform=system.pc
+system=system
+pio=system.iobus.port[7]
+
+[system.pc.south_bridge.speaker]
+type=PcSpeaker
+i8254=system.pc.south_bridge.pit
+pio_addr=9223372036854775905
+pio_latency=1000
+platform=system.pc
+system=system
+pio=system.iobus.port[8]
+
+[system.pc.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
+[system.smbios_table]
+type=X86SMBiosSMBiosTable
+children=structures
+major_version=2
+minor_version=5
+structures=system.smbios_table.structures
+
+[system.smbios_table.structures]
+type=X86SMBiosBiosInformation
+characteristic_ext_bytes=
+characteristics=
+emb_cont_firmware_major=0
+emb_cont_firmware_minor=0
+major=0
+minor=0
+release_date=06/08/2008
+rom_size=0
+starting_addr_segment=0
+vendor=
+version=
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
+
--- /dev/null
+warn: Sockets disabled, not accepting terminal connections
+For more information see: http://www.m5sim.org/warn/8742226b
+warn: Reading current count from inactive timer.
+For more information see: http://www.m5sim.org/warn/1ea2be46
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Don't know what interrupt to clear for console.
+For more information see: http://www.m5sim.org/warn/7fe1004f
+warn: instruction 'fxsave' unimplemented
+For more information see: http://www.m5sim.org/warn/437d5238
+warn: Tried to clear PCI interrupt 14
+For more information see: http://www.m5sim.org/warn/77378d57
+warn: Unknown mouse command 0xe1.
+For more information see: http://www.m5sim.org/warn/2447512a
+warn: instruction 'wbinvd' unimplemented
+For more information see: http://www.m5sim.org/warn/437d5238
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Feb 26 2011 16:13:31
+M5 revision 412ef0f728a5 8092 default qtip tip updatefsstats.patch
+M5 started Feb 26 2011 16:13:35
+M5 executing on burrito
+command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+ 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 5195470393000 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1546136 # Simulator instruction rate (inst/s)
+host_mem_usage 364716 # Number of bytes of host memory used
+host_seconds 170.97 # Real time elapsed on the host
+host_tick_rate 30388572127 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 264339287 # Number of instructions simulated
+sim_seconds 5.195470 # Number of seconds simulated
+sim_ticks 5195470393000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses::0 13288006 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13288006 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 15144.526649 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12144.494227 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_hits::0 11977182 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 11977182 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 19851809000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::0 0.098647 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 1310824 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1310824 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 15919294500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098647 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1310824 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 75925324500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_accesses::0 8347353 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 8347353 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 30172.881044 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27172.847747 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_hits::0 8032009 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 8032009 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 9514837000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::0 0.037778 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 315344 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 315344 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 8568794500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.037778 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 315344 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1379728500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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+system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
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+system.cpu.icache.tagsinuse 510.361283 # Cycle average of tags in use
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+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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+system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses)
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+system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits
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+system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.itb_walker_cache.avg_refs 2.005046 # Average number of references to valid blocks.
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+system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses
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+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 8042.372881 # average overall mshr miss latency
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+system.cpu.itb_walker_cache.demand_hits::1 7621 # number of demand (read+write) hits
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+system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use
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+system.cpu.itb_walker_cache.writebacks 826 # number of writebacks
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
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+system.cpu.numCycles 10390940786 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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+system.cpu.num_busy_cycles 603163545.121884 # Number of busy cycles
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+system.cpu.num_fp_insts 0 # number of float instructions
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+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_idle_cycles 9787777240.878117 # Number of idle cycles
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+system.cpu.num_int_insts 249556386 # number of integer instructions
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+system.cpu.num_load_insts 14812525 # Number of load instructions
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+system.cpu.num_store_insts 8357379 # Number of store instructions
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+system.iocache.tagsinuse 0.120586 # Cycle average of tags in use
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+system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit.
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+system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40254.930606 # average UpgradeReq mshr miss latency
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+system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits
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+system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 55109000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0 0.810539 # mshr miss rate for UpgradeReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses 1369 # number of UpgradeReq MSHR misses
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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+system.l2c.Writeback_accesses::0 1534567 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 1534567 # number of Writeback hits
+system.l2c.Writeback_hits::total 1534567 # number of Writeback hits
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+system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.l2c.avg_refs 19.991025 # Average number of references to valid blocks.
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.cache_copies 0 # number of cache copies performed
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+system.l2c.demand_avg_miss_latency::total 387245434.078463 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency
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+system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 8905447000 # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_rate::1 0.002400 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.073290 # miss rate for demand accesses
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+system.l2c.demand_misses::total 170998 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 6853449000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0 0.070900 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 17.842028 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 17.912929 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 170998 # number of demand (read+write) MSHR misses
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.occ_%::0 0.120711 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.358261 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 7910.895776 # Average occupied blocks per context
+system.l2c.occ_blocks::1 23478.999694 # Average occupied blocks per context
+system.l2c.overall_accesses::0 2411815 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 9584 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2421399 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 52086.252376 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 387193347.826087 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 387245434.078463 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.overall_hits::0 2240840 # number of overall hits
+system.l2c.overall_hits::1 9561 # number of overall hits
+system.l2c.overall_hits::total 2250401 # number of overall hits
+system.l2c.overall_miss_latency 8905447000 # number of overall miss cycles
+system.l2c.overall_miss_rate::0 0.070891 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.002400 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.073290 # miss rate for overall accesses
+system.l2c.overall_misses::0 170975 # number of overall misses
+system.l2c.overall_misses::1 23 # number of overall misses
+system.l2c.overall_misses::total 170998 # number of overall misses
+system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 6853449000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0 0.070900 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 17.842028 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 17.912929 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 170998 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 57269835000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.replacements 136133 # number of replacements
+system.l2c.sampled_refs 168244 # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use
+system.l2c.total_refs 3363370 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 116255 # number of writebacks
+system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
+system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
+
+---------- End Simulation Statistics ----------
--- /dev/null
+Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007\r
+Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
+BIOS-provided physical RAM map:\r
+ BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)\r
+ BIOS-e820: 0000000000100000 - 0000000008000000 (usable)\r
+end_pfn_map = 32768\r
+kernel direct mapping tables up to 8000000 @ 100000-102000\r
+DMI 2.5 present.\r
+Zone PFN ranges:\r
+ DMA 256 -> 4096\r
+ DMA32 4096 -> 1048576\r
+ Normal 1048576 -> 1048576\r
+early_node_map[1] active PFN ranges\r
+ 0: 256 -> 32768\r
+Intel MultiProcessor Specification v1.4\r
+MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000\r
+Processor #0 (Bootup-CPU)\r
+I/O APIC #1 at 0xFEC00000.\r
+Setting APIC routing to flat\r
+Processors: 1\r
+Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)\r
+Built 1 zonelists. Total pages: 30458\r
+Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
+Initializing CPU#0\r
+PID hash table entries: 512 (order: 9, 4096 bytes)\r
+time.c: Detected 1999.998 MHz processor.\r
+Console: colour dummy device 80x25\r
+console handover: boot [earlyser0] -> real [ttyS0]\r
+Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
+Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)\r
+Checking aperture...\r
+Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)\r
+Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
+Mount-cache hash table entries: 256\r
+CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
+CPU: L2 Cache: 1024K (64 bytes/line)\r
+CPU: Fake M5 x86_64 CPU stepping 01\r
+ACPI: Core revision 20070126\r
+ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]\r
+ACPI: Unable to load the System Description Tables\r
+Using local APIC timer interrupts.\r
+result 7812489\r
+Detected 7.812 MHz APIC timer.\r
+NET: Registered protocol family 16\r
+PCI: Using configuration type 1\r
+ACPI: Interpreter disabled.\r
+Linux Plug and Play Support v0.97 (c) Adam Belay\r
+pnp: PnP ACPI: disabled\r
+SCSI subsystem initialized\r
+usbcore: registered new interface driver usbfs\r
+usbcore: registered new interface driver hub\r
+usbcore: registered new device driver usb\r
+PCI: Probing PCI hardware\r
+PCI-GART: No AMD northbridge found.\r
+Time: tsc clocksource has been installed.\r
+NET: Registered protocol family 2\r
+IP route cache hash table entries: 1024 (order: 1, 8192 bytes)\r
+TCP established hash table entries: 4096 (order: 4, 65536 bytes)\r
+TCP bind hash table entries: 4096 (order: 3, 32768 bytes)\r
+TCP: Hash tables configured (established 4096 bind 4096)\r
+TCP reno registered\r
+Total HugeTLB memory allocated, 0\r
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).\r
+io scheduler noop registered\r
+io scheduler deadline registered\r
+io scheduler cfq registered (default)\r
+Real Time Clock Driver v1.12ac\r
+Linux agpgart interface v0.102 (c) Dave Jones\r
+Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled\r
+serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250\r
+floppy0: no floppy controllers found\r
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize\r
+loop: module loaded\r
+Intel(R) PRO/1000 Network Driver - version 7.3.20-k2\r
+Copyright (c) 1999-2006 Intel Corporation.\r
+e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI\r
+e100: Copyright(c) 1999-2006 Intel Corporation\r
+forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.\r
+tun: Universal TUN/TAP device driver, 1.6\r
+tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>\r
+netconsole: not configured, aborting\r
+Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2\r
+ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx\r
+PIIX4: IDE controller at PCI slot 0000:00:04.0\r
+PCI: Enabling device 0000:00:04.0 (0000 -> 0001)\r
+PIIX4: chipset revision 0\r
+PIIX4: not 100% native mode: will probe irqs later\r
+ ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA\r
+ ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA\r
+hda: M5 IDE Disk, ATA DISK drive\r
+hdb: M5 IDE Disk, ATA DISK drive\r
+ide0 at 0x1f0-0x1f7,0x3f6 on irq 14\r
+hda: max request size: 128KiB\r
+hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)\r
+ hda: hda1\r
+hdb: max request size: 128KiB\r
+hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)\r
+ hdb: unknown partition table\r
+megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)\r
+megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)\r
+megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007\r
+Fusion MPT base driver 3.04.04\r
+Copyright (c) 1999-2007 LSI Logic Corporation\r
+Fusion MPT SPI Host driver 3.04.04\r
+Fusion MPT SAS Host driver 3.04.04\r
+ieee1394: raw1394: /dev/raw1394 device initialized\r
+USB Universal Host Controller Interface driver v3.0\r
+usbcore: registered new interface driver usblp\r
+drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver\r
+Initializing USB Mass Storage driver...\r
+usbcore: registered new interface driver usb-storage\r
+USB Mass Storage support registered.\r
+PNP: No PS/2 controller found. Probing ports directly.\r
+serio: i8042 KBD port at 0x60,0x64 irq 1\r
+serio: i8042 AUX port at 0x60,0x64 irq 12\r
+mice: PS/2 mouse device common for all mice\r
+input: AT Translated Set 2 keyboard as /class/input/input0\r
+device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com\r
+input: PS/2 Generic Mouse as /class/input/input1\r
+usbcore: registered new interface driver usbhid\r
+drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver\r
+oprofile: using timer interrupt.\r
+TCP cubic registered\r
+NET: Registered protocol family 1\r
+NET: Registered protocol family 10\r
+IPv6 over IPv4 tunneling driver\r
+NET: Registered protocol family 17\r
+EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended\r
+VFS: Mounted root (ext2 filesystem).\r
+Freeing unused kernel memory: 232k freed\r
+\rINIT: version 2.86 booting\r\r
+mounting filesystems...\r
+loading script...\r
projects / gem5.git / commitdiff