* gcc.c-torture/compile/20040824-1.c: New test.

From-SVN: r86513

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 71573960708a1f7939b9d346e59f87838db2054c..be76cee5dc8718a8fda06f66010731069e3f7b08 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2004-08-24  Richard Sandiford  <rsandifo@redhat.com>
+
+       * gcc.c-torture/compile/20040824-1.c: New test.
+
 2004-08-24  Richard Earnshaw  <rearnsha@arm.com>
 
        * arm.md: Include predicates.md.

diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index 6b785fac62c177db7575e91287644a9cfdd22fe3..177da63bd135ce42e727eb219810001325e579fc 100644 (file)
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -203,7 +203,7 @@ extern const char *mips_output_conditional_branch (rtx, rtx *, int, int,
 extern const char *mips_output_division (const char *, rtx *);
 extern unsigned int mips_hard_regno_nregs (int, enum machine_mode);
 extern bool mips_linked_madd_p (rtx, rtx);
-extern const char *mips_emit_prefetch (rtx *);
+extern rtx mips_prefetch_cookie (rtx, rtx);
 
 extern void irix_asm_output_align (FILE *, unsigned);
 extern const char *current_section_name (void);

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 9f0bf68fadedb49a854c0320fee9cf56913a74cd..022d7b443ad52333825a5b970f98d5cb9a38be8a 100644 (file)
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -4836,6 +4836,10 @@ print_operand_address (FILE *file, rtx x)
        return;
 
       case ADDRESS_CONST_INT:
+       output_addr_const (file, x);
+       fprintf (file, "(%s)", reg_names[0]);
+       return;
+
       case ADDRESS_SYMBOLIC:
        output_addr_const (file, x);
        return;
@@ -9080,26 +9084,22 @@ mips_multipass_dfa_lookahead (void)
   return 0;
 }
 \f
+/* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
+   return the first operand of the associated "pref" or "prefx" insn.  */
 
-const char *
-mips_emit_prefetch (rtx *operands)
-{
-  int write = INTVAL (operands[1]);
-  int locality = INTVAL (operands[2]);
-  int indexed = GET_CODE (operands[3]) == REG;
-  int code;
-  char buffer[30];
-
-  if (locality <= 0)
-    code = (write ? 5 : 4);    /* store_streamed / load_streamed.  */
-  else if (locality <= 2)
-    code = (write ? 1 : 0);    /* store / load.  */
-  else
-    code = (write ? 7 : 6);    /* store_retained / load_retained.  */
+rtx
+mips_prefetch_cookie (rtx write, rtx locality)
+{
+  /* store_streamed / load_streamed.  */
+  if (INTVAL (locality) <= 0)
+    return GEN_INT (INTVAL (write) + 4);
+
+  /* store / load.  */
+  if (INTVAL (locality) <= 2)
+    return write;
 
-  sprintf (buffer, "%s\t%d,%%3(%%0)", indexed ? "prefx" : "pref", code);
-  output_asm_insn (buffer, operands);
-  return "";
+  /* store_retained / load_retained.  */
+  return GEN_INT (INTVAL (write) + 6);
 }
 
 #include "gt-mips.h"

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 46ec8cf1be1ced0f62ac335d51b2ad954735d8fd..b0179d97022571f1c1caf8742e2544f3d01f072c 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -5975,73 +5975,28 @@ beq\t%2,%.,1b\;\
 ;;
 
 
-(define_expand "prefetch"
-  [(prefetch (match_operand 0 "address_operand")
-            (match_operand 1 "const_int_operand")
-            (match_operand 2 "const_int_operand"))]
-  "ISA_HAS_PREFETCH"
-{
-  if (symbolic_operand (operands[0], GET_MODE (operands[0])))
-    operands[0] = force_reg (GET_MODE (operands[0]), operands[0]);
-})
-
-(define_insn "prefetch_si_address"
-  [(prefetch (plus:SI (match_operand:SI 0 "register_operand" "r")
-                     (match_operand:SI 3 "const_int_operand" "I"))
-            (match_operand:SI 1 "const_int_operand" "n")
-            (match_operand:SI 2 "const_int_operand" "n"))]
-  "ISA_HAS_PREFETCH && Pmode == SImode"
-  { return mips_emit_prefetch (operands); }
-  [(set_attr "type" "prefetch")])
-
-(define_insn "prefetch_indexed_si"
-  [(prefetch (plus:SI (match_operand:SI 0 "register_operand" "r")
-                     (match_operand:SI 3 "register_operand" "r"))
-            (match_operand:SI 1 "const_int_operand" "n")
-            (match_operand:SI 2 "const_int_operand" "n"))]
-  "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && Pmode == SImode"
-  { return mips_emit_prefetch (operands); }
-  [(set_attr "type" "prefetchx")])
-
-(define_insn "prefetch_si"
-  [(prefetch (match_operand:SI 0 "register_operand" "r")
-            (match_operand:SI 1 "const_int_operand" "n")
-            (match_operand:SI 2 "const_int_operand" "n"))]
-  "ISA_HAS_PREFETCH && Pmode == SImode"
-{
-  operands[3] = const0_rtx;
-  return mips_emit_prefetch (operands);
+(define_insn "prefetch"
+  [(prefetch (match_operand:QI 0 "address_operand" "p")
+            (match_operand 1 "const_int_operand" "n")
+            (match_operand 2 "const_int_operand" "n"))]
+  "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
+{
+  operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
+  return "pref\t%1,%a0";
 }
   [(set_attr "type" "prefetch")])
 
-(define_insn "prefetch_di_address"
-  [(prefetch (plus:DI (match_operand:DI 0 "register_operand" "r")
-                     (match_operand:DI 3 "const_int_operand" "I"))
-            (match_operand:DI 1 "const_int_operand" "n")
-            (match_operand:DI 2 "const_int_operand" "n"))]
-  "ISA_HAS_PREFETCH && Pmode == DImode"
-  { return mips_emit_prefetch (operands); }
-  [(set_attr "type" "prefetch")])
-
-(define_insn "prefetch_indexed_di"
-  [(prefetch (plus:DI (match_operand:DI 0 "register_operand" "r")
-                     (match_operand:DI 3 "register_operand" "r"))
-            (match_operand:DI 1 "const_int_operand" "n")
-            (match_operand:DI 2 "const_int_operand" "n"))]
-  "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && Pmode == DImode"
-  { return mips_emit_prefetch (operands); }
-  [(set_attr "type" "prefetchx")])
-
-(define_insn "prefetch_di"
-  [(prefetch (match_operand:DI 0 "register_operand" "r")
-            (match_operand:DI 1 "const_int_operand" "n")
-            (match_operand:DI 2 "const_int_operand" "n"))]
-  "ISA_HAS_PREFETCH && Pmode == DImode"
+(define_insn "*prefetch_indexed_<mode>"
+  [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
+                    (match_operand:P 1 "register_operand" "d"))
+            (match_operand 2 "const_int_operand" "n")
+            (match_operand 3 "const_int_operand" "n"))]
+  "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
 {
-  operands[3] = const0_rtx;
-  return mips_emit_prefetch (operands);
+  operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
+  return "prefx\t%2,%1(%0)";
 }
-  [(set_attr "type" "prefetch")])
+  [(set_attr "type" "prefetchx")])
 
 (define_insn "nop"
   [(const_int 0)]

diff --git a/gcc/testsuite/gcc.c-torture/compile/20040824-1.c b/gcc/testsuite/gcc.c-torture/compile/20040824-1.c
new file mode 100644 (file)
index 0000000..7d81932
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/20040824-1.c
@@ -0,0 +1,2 @@
+/* This caused an out-of-range address on the MIPS port.  */
+void foo (char *x) { __builtin_prefetch (x + 0x8000); }