arch-riscv: make sure only supported modes can be set in SATP.

Change-Id: I37c67e491d64bf03d1125e23db28611fa0b16038
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26983
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index ca3358e6f4cd51af8145e8bbe800b4c977bfce87..a71733bcb9e90ea5e61a9f8902ca56e67e7bd2f5 100644 (file)
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2016 RISC-V Foundation
  * Copyright (c) 2016 The University of Virginia
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -34,6 +35,7 @@
 #include <sstream>
 
 #include "arch/riscv/interrupts.hh"
+#include "arch/riscv/pagetable.hh"
 #include "arch/riscv/registers.hh"
 #include "base/bitfield.hh"
 #include "cpu/base.hh"
@@ -204,6 +206,18 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
                 ic->setIE(val);
             }
             break;
+          case MISCREG_SATP:
+            {
+                // we only support bare and Sv39 mode; setting a different mode
+                // shall have no effect (see 4.1.12 in priv ISA manual)
+                SATP cur_val = readMiscRegNoEffect(misc_reg);
+                SATP new_val = val;
+                if (new_val.mode != AddrXlateMode::BARE &&
+                    new_val.mode != AddrXlateMode::SV39)
+                    new_val.mode = cur_val.mode;
+                setMiscRegNoEffect(misc_reg, new_val);
+            }
+            break;
           default:
             setMiscRegNoEffect(misc_reg, val);
         }