src/cpu/ozone/cpu.hh:
Fixes to get OzoneCPU working in SE/FS again.
src/cpu/ozone/cpu_impl.hh:
Be sure to set up ports properly.
src/cpu/ozone/front_end.hh:
Allow port to be created without specifying its name at the beginning.
src/cpu/ozone/front_end_impl.hh:
Setup port properly, also only use checker if it's enabled.
src/cpu/ozone/lw_back_end_impl.hh:
Be sure to initialize variables.
src/cpu/ozone/lw_lsq.hh:
Handle locked flag for UP systems.
src/cpu/ozone/lw_lsq_impl.hh:
Initialize all variables.
src/python/m5/objects/OzoneCPU.py:
Fix up config.
--HG--
extra : convert_revision :
c99e7bf82fc0dd1099c7a82eaebd58ab6017764d
uint64_t readNextNPC()
{
- panic("Alpha has no NextNPC!");
return 0;
}
void setNextNPC(uint64_t val)
- { panic("Alpha has no NextNPC!"); }
+ { }
public:
// ISA stuff:
backEnd->renameTable.copyFrom(thread.renameTable);
#if !FULL_SYSTEM
-// pTable = p->pTable;
+ /* Use this port to for syscall emulation writes to memory. */
+ Port *mem_port;
+ TranslatingPort *trans_port;
+ trans_port = new TranslatingPort(csprintf("%s-%d-funcport",
+ name(), 0),
+ p->workload[0]->pTable,
+ false);
+ mem_port = p->mem->getPort("functional");
+ mem_port->setPeer(trans_port);
+ trans_port->setPeer(mem_port);
+ thread.setMemPort(trans_port);
+#else
+ Port *mem_port;
+ FunctionalPort *phys_port;
+ VirtualPort *virt_port;
+ phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
+ name(), 0));
+ mem_port = system->physmem->getPort("functional");
+ mem_port->setPeer(phys_port);
+ phys_port->setPeer(mem_port);
+
+ virt_port = new VirtualPort(csprintf("%s-%d-vport",
+ name(), 0));
+ mem_port = system->physmem->getPort("functional");
+ mem_port->setPeer(virt_port);
+ virt_port->setPeer(mem_port);
+
+ thread.setPhysPort(phys_port);
+ thread.setVirtPort(virt_port);
#endif
lockFlag = 0;
#include "sim/stats.hh"
class ThreadContext;
-class MemInterface;
+class MemObject;
template <class>
class OzoneThreadState;
class PageTable;
public:
/** Default constructor. */
IcachePort(FrontEnd<Impl> *_fe)
- : Port(_fe->name() + "-iport"), fe(_fe)
+ : fe(_fe)
{ }
protected:
std::string name() const;
- void setCPU(CPUType *cpu_ptr)
- { cpu = cpu_ptr; }
+ void setCPU(CPUType *cpu_ptr);
void setBackEnd(BackEnd *back_end_ptr)
{ backEnd = back_end_ptr; }
IcachePort icachePort;
+ MemObject *mem;
+
RequestPtr memReq;
/** Mask to get a cache block's address. */
* Authors: Kevin Lim
*/
+#include "config/use_checker.hh"
+
#include "arch/faults.hh"
#include "arch/isa_traits.hh"
#include "base/statistics.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
+#if USE_CHECKER
+#include "cpu/checker/cpu.hh"
+#endif
+
using namespace TheISA;
template<class Impl>
FrontEnd<Impl>::FrontEnd(Params *params)
: branchPred(params),
icachePort(this),
+ mem(params->mem),
instBufferSize(0),
maxInstBufferSize(params->maxInstBufferSize),
width(params->frontEndWidth),
return cpu->name() + ".frontend";
}
+template <class Impl>
+void
+FrontEnd<Impl>::setCPU(CPUType *cpu_ptr)
+{
+ cpu = cpu_ptr;
+
+ icachePort.setName(this->name() + "-iport");
+
+ Port *mem_dport = mem->getPort("");
+ icachePort.setPeer(mem_dport);
+ mem_dport->setPeer(&icachePort);
+
+#if USE_CHECKER
+ if (cpu->checker) {
+ cpu->checker->setIcachePort(&icachePort);
+ }
+#endif
+}
+
template <class Impl>
void
FrontEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
template <class Impl>
LWBackEnd<Impl>::LWBackEnd(Params *params)
: d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(5, 5),
- trapSquash(false), tcSquash(false),
+ trapSquash(false), tcSquash(false), LSQ(params),
width(params->backEndWidth), exactFullStall(true)
{
numROBEntries = params->numROBEntries;
LSQ.init(params, params->LQEntries, params->SQEntries, 0);
dispatchStatus = Running;
+ commitStatus = Running;
}
template <class Impl>
return NoFault;
}
+ if (req->getFlags() & LOCKED) {
+ cpu->lockFlag = true;
+ }
+
if (data_pkt->result != Packet::Success) {
DPRINTF(OzoneLSQ, "OzoneLSQ: D-cache miss!\n");
DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
template <class Impl>
OzoneLWLSQ<Impl>::OzoneLWLSQ()
- : loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false),
- loadBlockedHandled(false)
+ : switchedOut(false), loads(0), stores(0), storesToWB(0), stalled(false),
+ isStoreBlocked(false), isLoadBlocked(false), loadBlockedHandled(false)
{
}
SQIndices.push(i);
}
+ mem = params->mem;
+
usedPorts = 0;
cachePorts = params->cachePorts;
numThreads = Param.Unsigned("number of HW thread contexts")
- if not build_env['FULL_SYSTEM']:
- mem = Param.FunctionalMemory(NULL, "memory")
-
checker = Param.BaseCPU("Checker CPU")
width = Param.Unsigned("Width")