i965: Add separate stencil/HiZ setup for MESA_FORMAT_Z32_FLOAT_X24S8.

This is a little more unusual than the separate MESA_FORMAT_S8_Z24
support, because in addition to storing the real stencil data in a
MESA_FORMAT_S8 miptree, we also make the Z miptree be
MESA_FORMAT_Z32_FLOAT instead of the requested format.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 8a6a694bcce6533e9216644af7d946e4df1066e9..ad49c8fe688f193d9975b674cbbe75554655b017 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -216,7 +216,7 @@ brw_depthbuffer_format(struct brw_context *brw)
    if (!drb)
       return BRW_DEPTHFORMAT_D32_FLOAT;
 
-   switch (drb->Base.Format) {
+   switch (drb->mt->format) {
    case MESA_FORMAT_Z16:
       return BRW_DEPTHFORMAT_D16_UNORM;
    case MESA_FORMAT_Z32_FLOAT:

diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index bc76ec23749a58211bf2d25de10575f428883c9e..d34880659e2c10b90783b24ded2cda93d31f14c0 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -202,6 +202,8 @@ static bool brw_is_hiz_depth_format(struct intel_context *intel,
       return false;
 
    switch (format) {
+   case MESA_FORMAT_Z32_FLOAT:
+   case MESA_FORMAT_Z32_FLOAT_X24S8:
    case MESA_FORMAT_X8_Z24:
    case MESA_FORMAT_S8_Z24:
       return true;

diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 0d49fec43d42ebe1abd53a1fb5b934f9179e6633..e0f9632838b56131ba5b6e25ded2d5908aef4bb8 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -89,9 +89,6 @@ intel_miptree_create_internal(struct intel_context *intel,
    mt->compressed = compress_byte ? 1 : 0;
    mt->refcount = 1; 
 
-   intel_get_texture_alignment_unit(intel, format,
-                                   &mt->align_w, &mt->align_h);
-
    if (target == GL_TEXTURE_CUBE_MAP) {
       assert(depth0 == 1);
       mt->depth0 = 6;
@@ -109,16 +106,6 @@ intel_miptree_create_internal(struct intel_context *intel,
       mt->cpp = 2;
    }
 
-#ifdef I915
-   (void) intel;
-   if (intel->is_945)
-      i945_miptree_layout(mt);
-   else
-      i915_miptree_layout(mt);
-#else
-   brw_miptree_layout(intel, mt);
-#endif
-
    if (_mesa_is_depthstencil_format(_mesa_get_format_base_format(format)) &&
        (intel->must_use_separate_stencil ||
        (intel->has_separate_stencil &&
@@ -142,12 +129,28 @@ intel_miptree_create_internal(struct intel_context *intel,
        */
       if (mt->format == MESA_FORMAT_S8_Z24) {
         mt->format = MESA_FORMAT_X8_Z24;
+      } else if (mt->format == MESA_FORMAT_Z32_FLOAT_X24S8) {
+        mt->format = MESA_FORMAT_Z32_FLOAT;
+        mt->cpp = 4;
       } else {
-        _mesa_problem("Unknown format %s in separate stencil\n",
+        _mesa_problem(NULL, "Unknown format %s in separate stencil mt\n",
                       _mesa_get_format_name(mt->format));
       }
    }
 
+   intel_get_texture_alignment_unit(intel, mt->format,
+                                   &mt->align_w, &mt->align_h);
+
+#ifdef I915
+   (void) intel;
+   if (intel->is_945)
+      i945_miptree_layout(mt);
+   else
+      i915_miptree_layout(mt);
+#else
+   brw_miptree_layout(intel, mt);
+#endif
+
    return mt;
 }