latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Sep 24 2009 12:19:09
-M5 revision 9bc3e4611009+ 6661+ default tip
-M5 started Sep 24 2009 12:19:46
-M5 executing on zooks
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing
+M5 compiled Dec 29 2009 23:25:57
+M5 revision b49d467587f8 6811 default processinit.patch qtip tip
+M5 started Dec 29 2009 23:25:59
+M5 executing on fajita
+command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 29521500 because target called exit()
+Exiting @ tick 29940500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 29581 # Simulator instruction rate (inst/s)
-host_mem_usage 155804 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
-host_tick_rate 153369596 # Simulator tick rate (ticks/s)
+host_inst_rate 2950 # Simulator instruction rate (inst/s)
+host_mem_usage 204636 # Number of bytes of host memory used
+host_seconds 1.98 # Real time elapsed on the host
+host_tick_rate 15157943 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5685 # Number of instructions simulated
+sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000030 # Number of seconds simulated
-sim_ticks 29521500 # Number of ticks simulated
-system.cpu.AGEN-Unit.instReqsProcessed 2058 # Number of Instructions Requests that completed in this resource.
-system.cpu.Branch-Predictor.instReqsProcessed 5686 # Number of Instructions Requests that completed in this resource.
-system.cpu.Branch-Predictor.predictedNotTaken 789 # Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken 96 # Number of Branches Predicted As Taken (True).
-system.cpu.Decode-Unit.instReqsProcessed 5686 # Number of Instructions Requests that completed in this resource.
-system.cpu.Execution-Unit.instReqsProcessed 3624 # Number of Instructions Requests that completed in this resource.
-system.cpu.Execution-Unit.predictedNotTakenIncorrect 516 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.Execution-Unit.predictedTakenIncorrect 34 # Number of Branches Incorrectly Predicted As Taken.
+sim_ticks 29940500 # Number of ticks simulated
+system.cpu.AGEN-Unit.instReqsProcessed 2090 # Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.instReqsProcessed 5828 # Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.predictedNotTaken 826 # Number of Branches Predicted As Not Taken (False).
+system.cpu.Branch-Predictor.predictedTaken 90 # Number of Branches Predicted As Taken (True).
+system.cpu.Decode-Unit.instReqsProcessed 5828 # Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.instReqsProcessed 3734 # Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.predictedNotTakenIncorrect 541 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.Execution-Unit.predictedTakenIncorrect 35 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Fetch-Buffer-T0.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource.
system.cpu.Fetch-Buffer-T0.instsBypassed 0 # Number of Instructions Bypassed.
system.cpu.Fetch-Buffer-T1.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource.
system.cpu.Fetch-Buffer-T1.instsBypassed 0 # Number of Instructions Bypassed.
-system.cpu.Fetch-Seq-Unit.instReqsProcessed 11373 # Number of Instructions Requests that completed in this resource.
-system.cpu.Graduation-Unit.instReqsProcessed 5685 # Number of Instructions Requests that completed in this resource.
+system.cpu.Fetch-Seq-Unit.instReqsProcessed 11657 # Number of Instructions Requests that completed in this resource.
+system.cpu.Graduation-Unit.instReqsProcessed 5827 # Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.divInstReqsProcessed 1 # Number of Divide Requests Processed.
system.cpu.Mult-Div-Unit.instReqsProcessed 8 # Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.multInstReqsProcessed 3 # Number of Multiply Requests Processed.
-system.cpu.RegFile-Manager.instReqsProcessed 10479 # Number of Instructions Requests that completed in this resource.
-system.cpu.committedInsts 5685 # Number of Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total 5685 # Number of Instructions Simulated (Total)
-system.cpu.cpi 10.385928 # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 10.385928 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1134 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56207.317073 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53207.317073 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1052 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4609000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.072310 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4363000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.072310 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
+system.cpu.RegFile-Manager.instReqsProcessed 10713 # Number of Instructions Requests that completed in this resource.
+system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total)
+system.cpu.cpi 10.276643 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 10.276643 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1165 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 56201.149425 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53201.149425 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1078 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4889500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.074678 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 4628500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.074678 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56554.687500 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53554.687500 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits 861 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 3619500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.069189 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 3427500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 14.590909 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 14.144928 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2058 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56359.589041 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53359.589041 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1912 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 8228500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.070943 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses 2090 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 56350.993377 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53350.993377 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1939 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 8509000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.072249 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 151 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7790500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.070943 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 8056000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.072249 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2058 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56359.589041 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53359.589041 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 2090 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 56350.993377 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53350.993377 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1912 # number of overall hits
-system.cpu.dcache.overall_miss_latency 8228500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.070943 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 146 # number of overall misses
+system.cpu.dcache.overall_hits 1939 # number of overall hits
+system.cpu.dcache.overall_miss_latency 8509000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.072249 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 151 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7790500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.070943 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 8056000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.072249 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 84.209307 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1926 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 88.212490 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1952 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dcache_port.instReqsProcessed 2057 # Number of Instructions Requests that completed in this resource.
+system.cpu.dcache_port.instReqsProcessed 2089 # Number of Instructions Requests that completed in this resource.
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 5687 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55773.026316 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52773.026316 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 5383 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 16955000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.053455 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 304 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 16043000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.053455 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 304 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55765.676568 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52765.676568 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 16897000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 15988000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 17.707237 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 5687 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55773.026316 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52773.026316 # average overall mshr miss latency
-system.cpu.icache.demand_hits 5383 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 16955000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.053455 # miss rate for demand accesses
-system.cpu.icache.demand_misses 304 # number of demand (read+write) misses
+system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55765.676568 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52765.676568 # average overall mshr miss latency
+system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 16897000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses
+system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 16043000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.053455 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 304 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_miss_latency 15988000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 5687 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55773.026316 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52773.026316 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55765.676568 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52765.676568 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 5383 # number of overall hits
-system.cpu.icache.overall_miss_latency 16955000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.053455 # miss rate for overall accesses
-system.cpu.icache.overall_misses 304 # number of overall misses
+system.cpu.icache.overall_hits 5526 # number of overall hits
+system.cpu.icache.overall_miss_latency 16897000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses
+system.cpu.icache.overall_misses 303 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 16043000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.053455 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 304 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_miss_latency 15988000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 13 # number of replacements
-system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 136.385131 # Cycle average of tags in use
-system.cpu.icache.total_refs 5383 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 134.267603 # Cycle average of tags in use
+system.cpu.icache.total_refs 5526 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache_port.instReqsProcessed 5686 # Number of Instructions Requests that completed in this resource.
-system.cpu.ipc 0.096284 # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 0.096284 # IPC: Total IPC of All Threads
+system.cpu.icache_port.instReqsProcessed 5828 # Number of Instructions Requests that completed in this resource.
+system.cpu.ipc 0.097308 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.097308 # IPC: Total IPC of All Threads
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52500 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40080 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2625000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40098.039216 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2677500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2004000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2045000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 386 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52052.083333 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40026.041667 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52052.835052 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40023.195876 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 19988000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.994819 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 384 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 15370000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994819 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52535.714286 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40071.428571 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 735500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 20196500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 15529000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52538.461538 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40076.923077 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 683000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 561000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 521000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.005405 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.005333 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52103.686636 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40032.258065 # average overall mshr miss latency
+system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52104.783599 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40031.890661 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 22613000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995413 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 434 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency 22874000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 17374000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.995413 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 434 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 17574000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52103.686636 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40032.258065 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52104.783599 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40031.890661 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 22613000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995413 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 434 # number of overall misses
+system.cpu.l2cache.overall_miss_latency 22874000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 439 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 17374000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.995413 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 434 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 17574000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 370 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 375 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 183.672228 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 185.807591 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 59044 # number of cpu cycles simulated
+system.cpu.numCycles 59882 # number of cpu cycles simulated
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was simultaneous multithreading.(SMT)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
-system.cpu.threadCycles 59044 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
-system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
+system.cpu.threadCycles 59882 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Sep 24 2009 12:19:09
-M5 revision 9bc3e4611009+ 6661+ default tip
-M5 started Sep 24 2009 12:19:46
-M5 executing on zooks
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing
+M5 compiled Dec 29 2009 23:25:57
+M5 revision b49d467587f8 6811 default processinit.patch qtip tip
+M5 started Dec 29 2009 23:25:59
+M5 executing on fajita
+command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 13914500 because target called exit()
+Exiting @ tick 14060500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 59567 # Simulator instruction rate (inst/s)
-host_mem_usage 155776 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
-host_tick_rate 163592222 # Simulator tick rate (ticks/s)
+host_inst_rate 2622 # Simulator instruction rate (inst/s)
+host_mem_usage 204532 # Number of bytes of host memory used
+host_seconds 1.97 # Real time elapsed on the host
+host_tick_rate 7130320 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5049 # Number of instructions simulated
+sim_insts 5169 # Number of instructions simulated
sim_seconds 0.000014 # Number of seconds simulated
-sim_ticks 13914500 # Number of ticks simulated
+sim_ticks 14060500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 552 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 1939 # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 722 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 1555 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 2357 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 387 # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches 885 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 63 # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits 572 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 1960 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 751 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 1593 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 2416 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 404 # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 916 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 65 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 14230 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.399438 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.125719 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 14561 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.400110 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.121131 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0-1 11753 82.59% 82.59% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1-2 1168 8.21% 90.80% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2-3 499 3.51% 94.31% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3-4 284 2.00% 96.30% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4-5 291 2.04% 98.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5-6 72 0.51% 98.85% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6-7 62 0.44% 99.29% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7-8 38 0.27% 99.56% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 63 0.44% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0-1 11999 82.41% 82.41% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1-2 1213 8.33% 90.74% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2-3 529 3.63% 94.37% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3-4 291 2.00% 96.37% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4-5 294 2.02% 98.39% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5-6 71 0.49% 98.87% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6-7 62 0.43% 99.30% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7-8 37 0.25% 99.55% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 65 0.45% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 14230 # Number of insts commited each cycle
-system.cpu.commit.COM:count 5684 # Number of instructions committed
-system.cpu.commit.COM:loads 1133 # Number of loads committed
+system.cpu.commit.COM:committed_per_cycle::total 14561 # Number of insts commited each cycle
+system.cpu.commit.COM:count 5826 # Number of instructions committed
+system.cpu.commit.COM:loads 1164 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 2057 # Number of memory references committed
+system.cpu.commit.COM:refs 2089 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 605 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5684 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 15 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 5973 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5049 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5049 # Number of Instructions Simulated
-system.cpu.cpi 5.511983 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.511983 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 2297 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 34007.812500 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36022.988506 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 2169 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4353000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.055725 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 3134000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.037875 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27701.724138 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36093.750000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 634 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 8033500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.313853 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 290 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 226 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2310000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
+system.cpu.commit.branchMispredicts 620 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 6017 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 5169 # Number of Instructions Simulated
+system.cpu.committedInsts_total 5169 # Number of Instructions Simulated
+system.cpu.cpi 5.440511 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.440511 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 2321 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 34074.626866 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36043.956044 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 2187 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4566000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.057734 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 3280000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.039207 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 27570.707071 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36046.875000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 628 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 8188500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.321081 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 297 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 233 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2307000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 20.889706 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 20.226950 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 3221 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 29632.775120 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 36052.980132 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2803 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 12386500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.129773 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 418 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 5444000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.046880 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 3246 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 29592.807425 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2815 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 12754500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.132779 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 431 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 276 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 5587000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.047751 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 3221 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 29632.775120 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 36052.980132 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 3246 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 29592.807425 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2803 # number of overall hits
-system.cpu.dcache.overall_miss_latency 12386500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.129773 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 418 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 267 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 5444000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.046880 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 2815 # number of overall hits
+system.cpu.dcache.overall_miss_latency 12754500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.132779 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 431 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 276 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 5587000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.047751 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 136 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 87.690614 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2841 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 91.308954 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2852 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 479 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 128 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 128 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 14211 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 9912 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 3839 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1056 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 251 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:BlockedCycles 519 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 139 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 139 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 14436 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 10077 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 3965 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1080 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 267 # Number of squashed instructions handled by decode
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.fetch.Branches 2357 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 2171 # Number of cache lines fetched
-system.cpu.fetch.Cycles 6187 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 360 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 15337 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 738 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.084693 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 2171 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 939 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.551096 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 15286 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.003336 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.263199 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches 2416 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 2220 # Number of cache lines fetched
+system.cpu.fetch.Cycles 6371 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 355 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 15622 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 767 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.085911 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 2220 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.555508 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 15641 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.998785 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.252974 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0-1 11277 73.77% 73.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1-2 1770 11.58% 85.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2-3 198 1.30% 86.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3-4 138 0.90% 87.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4-5 316 2.07% 89.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5-6 114 0.75% 90.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6-7 306 2.00% 92.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7-8 249 1.63% 93.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 918 6.01% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0-1 11507 73.57% 73.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1-2 1847 11.81% 85.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2-3 223 1.43% 86.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3-4 141 0.90% 87.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4-5 312 1.99% 89.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5-6 120 0.77% 90.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6-7 308 1.97% 92.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7-8 254 1.62% 94.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 929 5.94% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 15286 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 2171 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35436.489607 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34915.151515 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1738 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 15344000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.199447 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 433 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 103 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 11522000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.152004 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 330 # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total 15641 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 2220 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35681.279621 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34902.735562 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1798 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 15057500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.190090 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 422 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 93 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 11483000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.148198 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 5.266667 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 5.465046 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 2171 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35436.489607 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34915.151515 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1738 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 15344000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.199447 # miss rate for demand accesses
-system.cpu.icache.demand_misses 433 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 11522000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.152004 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 330 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 2220 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35681.279621 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1798 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 15057500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.190090 # miss rate for demand accesses
+system.cpu.icache.demand_misses 422 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 93 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 11483000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.148198 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 2171 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35436.489607 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34915.151515 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 2220 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35681.279621 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1738 # number of overall hits
-system.cpu.icache.overall_miss_latency 15344000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.199447 # miss rate for overall accesses
-system.cpu.icache.overall_misses 433 # number of overall misses
-system.cpu.icache.overall_mshr_hits 103 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 11522000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.152004 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 330 # number of overall MSHR misses
+system.cpu.icache.overall_hits 1798 # number of overall hits
+system.cpu.icache.overall_miss_latency 15057500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.190090 # miss rate for overall accesses
+system.cpu.icache.overall_misses 422 # number of overall misses
+system.cpu.icache.overall_mshr_hits 93 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 11483000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.148198 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 16 # number of replacements
-system.cpu.icache.sampled_refs 330 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 159.086288 # Cycle average of tags in use
-system.cpu.icache.total_refs 1738 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 156.015053 # Cycle average of tags in use
+system.cpu.icache.total_refs 1798 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 12544 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 1216 # Number of branches executed
-system.cpu.iew.EXEC:nop 1820 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.292239 # Inst execution rate
-system.cpu.iew.EXEC:refs 3432 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 1048 # Number of stores executed
+system.cpu.idleCycles 12481 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 1253 # Number of branches executed
+system.cpu.iew.EXEC:nop 1830 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.295249 # Inst execution rate
+system.cpu.iew.EXEC:refs 3456 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 1049 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 4040 # num instructions consuming a value
-system.cpu.iew.WB:count 7355 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.694802 # average fanout of values written-back
+system.cpu.iew.WB:consumers 4132 # num instructions consuming a value
+system.cpu.iew.WB:count 7536 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.703291 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 2807 # num instructions producing a value
-system.cpu.iew.WB:rate 0.264283 # insts written-back per cycle
-system.cpu.iew.WB:sent 7444 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 663 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 8 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2795 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 15 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 968 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 11660 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 2384 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 531 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 8133 # Number of executed instructions
+system.cpu.iew.WB:producers 2906 # num instructions producing a value
+system.cpu.iew.WB:rate 0.267975 # insts written-back per cycle
+system.cpu.iew.WB:sent 7618 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 681 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 2806 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 963 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 11847 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 2407 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 549 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 8303 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1056 # Number of cycles IEW is squashing
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1080 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 22 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1662 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedLoads 1642 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 234 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 386 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.181423 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.181423 # IPC: Total IPC of All Threads
+system.cpu.iew.predictedNotTakenIncorrect 272 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 409 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.183806 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.183806 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 5020 57.94% 57.94% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 2572 29.69% 87.73% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 1063 12.27% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 5184 58.56% 58.56% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.62% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.64% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.66% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.66% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.66% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.66% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.66% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.66% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 2595 29.32% 87.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 1064 12.02% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 8664 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 8852 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.018698 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate 0.018301 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 10 6.17% 6.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 6.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 6.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 6.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 6.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 6.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 6.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 98 60.49% 66.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 8 4.94% 4.94% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.94% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.94% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.94% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.94% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.94% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.94% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.94% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.94% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 100 61.73% 66.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 54 33.33% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 15286 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.566793 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217668 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 15641 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.565948 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.209939 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0-1 11421 74.72% 74.72% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1-2 1678 10.98% 85.69% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2-3 792 5.18% 90.87% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3-4 722 4.72% 95.60% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4-5 333 2.18% 97.78% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5-6 200 1.31% 99.08% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6-7 91 0.60% 99.68% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.22% 99.90% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0-1 11653 74.50% 74.50% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1-2 1757 11.23% 85.74% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2-3 814 5.20% 90.94% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3-4 738 4.72% 95.66% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4-5 342 2.19% 97.85% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5-6 199 1.27% 99.12% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6-7 91 0.58% 99.70% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7-8 32 0.20% 99.90% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 15286 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.311319 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9825 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8664 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 15 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 4207 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 30 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedOperandsExamined 2761 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total 15641 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.314771 # Inst issue rate
+system.cpu.iq.iqInstsAdded 10005 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 8852 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 4214 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 36 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 2725 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 49 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34704.081633 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31408.163265 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 1700500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34680 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31360 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 1734000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 49 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1539000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1568000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 49 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 417 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34307.506053 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.750605 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 420 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.221154 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 14169000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.990408 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 413 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 12857000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990408 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 413 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34400 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31166.666667 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 516000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.990476 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 12953500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990476 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34428.571429 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31178.571429 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 482000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 467500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.010050 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.009950 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 466 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34349.567100 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31160.173160 # average overall mshr miss latency
+system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34356.223176 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 15869500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.991416 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 462 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency 16010000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.991489 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 466 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 14396000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.991416 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 462 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 14521500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.991489 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 466 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 466 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34349.567100 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31160.173160 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34356.223176 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 4 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 15869500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.991416 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 462 # number of overall misses
+system.cpu.l2cache.overall_miss_latency 16010000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.991489 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 466 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 14396000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.991416 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 462 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 14521500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.991489 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 466 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 398 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 402 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 209.158769 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 210.151573 # Cycle average of tags in use
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 2795 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 27830 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 20 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 3323 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 10291 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 16 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 15666 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 13454 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8251 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 3462 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1056 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 29 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4928 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 428 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 125 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 14 # count of temporary serializing insts renamed
-system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
+system.cpu.memDep0.insertedLoads 2806 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 28122 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 5 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IdleCycles 10468 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 9 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 15900 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 13681 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 8420 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 3575 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1080 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 19 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 5010 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 494 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 17 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 111 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed
+system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Sep 24 2009 12:19:09
-M5 revision 9bc3e4611009+ 6661+ default tip
-M5 started Sep 24 2009 12:19:47
-M5 executing on zooks
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic
+M5 compiled Dec 29 2009 23:25:57
+M5 revision b49d467587f8 6811 default processinit.patch qtip tip
+M5 started Dec 29 2009 23:25:59
+M5 executing on fajita
+command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 2842500 because target called exit()
+Exiting @ tick 2913500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 588083 # Simulator instruction rate (inst/s)
-host_mem_usage 149516 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 285563593 # Simulator tick rate (ticks/s)
+host_inst_rate 2846 # Simulator instruction rate (inst/s)
+host_mem_usage 196092 # Number of bytes of host memory used
+host_seconds 2.05 # Real time elapsed on the host
+host_tick_rate 1422983 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5685 # Number of instructions simulated
+sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
-sim_ticks 2842500 # Number of ticks simulated
+sim_ticks 2913500 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 5686 # number of cpu cycles simulated
-system.cpu.num_insts 5685 # Number of instructions executed
-system.cpu.num_refs 2058 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
+system.cpu.numCycles 5828 # number of cpu cycles simulated
+system.cpu.num_insts 5827 # Number of instructions executed
+system.cpu.num_refs 2090 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Sep 24 2009 12:19:09
-M5 revision 9bc3e4611009+ 6661+ default tip
-M5 started Sep 24 2009 12:19:31
-M5 executing on zooks
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing
+M5 compiled Dec 29 2009 23:25:57
+M5 revision b49d467587f8 6811 default processinit.patch qtip tip
+M5 started Dec 29 2009 23:25:59
+M5 executing on fajita
+command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 32409000 because target called exit()
+Exiting @ tick 32803000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 303832 # Simulator instruction rate (inst/s)
-host_mem_usage 155376 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 1703674499 # Simulator tick rate (ticks/s)
+host_inst_rate 2804 # Simulator instruction rate (inst/s)
+host_mem_usage 203720 # Number of bytes of host memory used
+host_seconds 2.08 # Real time elapsed on the host
+host_tick_rate 15782115 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5685 # Number of instructions simulated
-sim_seconds 0.000032 # Number of seconds simulated
-sim_ticks 32409000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 1133 # number of ReadReq accesses(hits+misses)
+sim_insts 5827 # Number of instructions simulated
+sim_seconds 0.000033 # Number of seconds simulated
+sim_ticks 32803000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1051 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4592000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.072374 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4346000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.072374 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4872000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 4611000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits 861 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 3584000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.069189 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 14.583333 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2057 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1911 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 8176000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.070977 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses
+system.cpu.dcache.demand_hits 1938 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 8456000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.072283 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 151 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7738000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.070977 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 8003000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.072283 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2057 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1911 # number of overall hits
-system.cpu.dcache.overall_miss_latency 8176000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.070977 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 146 # number of overall misses
+system.cpu.dcache.overall_hits 1938 # number of overall hits
+system.cpu.dcache.overall_miss_latency 8456000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.072283 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 151 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7738000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.070977 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 8003000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.072283 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 83.830110 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1925 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 87.887695 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 5687 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55723.684211 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52723.684211 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 5383 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 16940000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.053455 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 304 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 16028000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.053455 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 304 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 17.707237 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 5687 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55723.684211 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52723.684211 # average overall mshr miss latency
-system.cpu.icache.demand_hits 5383 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 16940000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.053455 # miss rate for demand accesses
-system.cpu.icache.demand_misses 304 # number of demand (read+write) misses
+system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
+system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses
+system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 16028000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.053455 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 304 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 5687 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55723.684211 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52723.684211 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 5383 # number of overall hits
-system.cpu.icache.overall_miss_latency 16940000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.053455 # miss rate for overall accesses
-system.cpu.icache.overall_misses 304 # number of overall misses
+system.cpu.icache.overall_hits 5526 # number of overall hits
+system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses
+system.cpu.icache.overall_misses 303 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 16028000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.053455 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 304 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 13 # number of replacements
-system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 135.394401 # Cycle average of tags in use
-system.cpu.icache.total_refs 5383 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 133.475693 # Cycle average of tags in use
+system.cpu.icache.total_refs 5526 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2600000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 2652000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2000000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 386 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 19968000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.994819 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 384 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 15360000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994819 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_miss_latency 20176000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 520000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.005405 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.005333 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995413 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 434 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency 22828000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 17360000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.995413 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 434 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 17560000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 22568000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995413 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 434 # number of overall misses
+system.cpu.l2cache.overall_miss_latency 22828000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 439 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 17360000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.995413 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 434 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 370 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 375 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 182.412916 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 184.758016 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 64818 # number of cpu cycles simulated
-system.cpu.num_insts 5685 # Number of instructions executed
-system.cpu.num_refs 2058 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
+system.cpu.numCycles 65606 # number of cpu cycles simulated
+system.cpu.num_insts 5827 # Number of instructions executed
+system.cpu.num_refs 2090 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff