arch-arm: TLBI ALLE2IS should broadcast to the IS domain

This was implemented as a normal ALLE2 hence affecting the
current PE only

Change-Id: Ib369dd5a4b738daf96a01b5535d7481a97bb3730
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34795
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9ace2367f4b0da3978301d29a71326809bb6d5d8..cfef0ab071e41790b85bb23a073c3f5535721068 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1711,9 +1711,8 @@ ISA::setMiscReg(int misc_reg, RegVal val)
                 tlbiOp.broadcast(tc);
                 return;
             }
-          // AArch64 TLB Invalidate All, EL2, Inner Shareable
+          // AArch64 TLB Invalidate All, EL2
           case MISCREG_TLBI_ALLE2:
-          case MISCREG_TLBI_ALLE2IS:
             {
                 assert64();
                 scr = readMiscReg(MISCREG_SCR);
@@ -1722,6 +1721,16 @@ ISA::setMiscReg(int misc_reg, RegVal val)
                 tlbiOp(tc);
                 return;
             }
+          // AArch64 TLB Invalidate All, EL2, Inner Shareable
+          case MISCREG_TLBI_ALLE2IS:
+            {
+                assert64();
+                scr = readMiscReg(MISCREG_SCR);
+
+                TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
+                tlbiOp.broadcast(tc);
+                return;
+            }
           // AArch64 TLB Invalidate All, EL1
           case MISCREG_TLBI_ALLE1:
           case MISCREG_TLBI_VMALLS12E1: