lm32: replace clogb2 by builtin $clog2

This function is fixed in ISE since version 14.1 (see AR #44586). If the
builtin function is used, the design can be simulated with Icarus Verilog.

Signed-off-by: Michael Walle <michael@walle.cc>

diff --git a/verilog/lm32/lm32_cpu.v b/verilog/lm32/lm32_cpu.v
index dc5be84c9a599132955cc60b958f56065a57830d..ee0daf43b7a78be4ab572b92b686c94cddd34bd8 100644 (file)
--- a/verilog/lm32/lm32_cpu.v
+++ b/verilog/lm32/lm32_cpu.v
@@ -780,8 +780,6 @@ reg ext_break_r;
 // Functions
 /////////////////////////////////////////////////////
 
-`include "lm32_functions.v"
-
 /////////////////////////////////////////////////////
 // Instantiations
 ///////////////////////////////////////////////////// 

diff --git a/verilog/lm32/lm32_dcache.v b/verilog/lm32/lm32_dcache.v
index 71e4c0bf37a8999277154abb7d4d54f25fd70431..7b3799e33c7bf692a80f405501dbf5bf211346a2 100644 (file)
--- a/verilog/lm32/lm32_dcache.v
+++ b/verilog/lm32/lm32_dcache.v
@@ -112,14 +112,14 @@ parameter bytes_per_line = 16;                          // Number of bytes per c
 parameter base_address = 0;                             // Base address of cachable memory
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
 
-localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
-localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_width = $clog2(bytes_per_line)-2;
+localparam addr_set_width = $clog2(sets);
 localparam addr_offset_lsb = 2;
 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
 localparam addr_set_lsb = (addr_offset_msb+1);
 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
 localparam addr_tag_lsb = (addr_set_msb+1);
-localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1;
+localparam addr_tag_msb = $clog2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS);
 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
 
 /////////////////////////////////////////////////////
@@ -200,8 +200,6 @@ genvar i, j;
 // Functions
 /////////////////////////////////////////////////////
 
-`include "lm32_functions.v"
-
 /////////////////////////////////////////////////////
 // Instantiations
 /////////////////////////////////////////////////////

diff --git a/verilog/lm32/lm32_debug.v b/verilog/lm32/lm32_debug.v
index 90c8d20be5a65f97749cd2cc20b2da1e3b708cd6..e7f73cb16e225c75a41d017752e4c78aebc98d5e 100644 (file)
--- a/verilog/lm32/lm32_debug.v
+++ b/verilog/lm32/lm32_debug.v
@@ -183,8 +183,6 @@ integer state;                                  // State of single-step FSM
 // Functions
 /////////////////////////////////////////////////////
 
-`include "lm32_functions.v"
-
 /////////////////////////////////////////////////////
 // Combinational Logic
 /////////////////////////////////////////////////////

diff --git a/verilog/lm32/lm32_decoder.v b/verilog/lm32/lm32_decoder.v
index eebe5c3efbbc563ef9094da21b1903352c04772e..be20c16e849864636cac29fdddae08098bd56b05 100644 (file)
--- a/verilog/lm32/lm32_decoder.v
+++ b/verilog/lm32/lm32_decoder.v
@@ -333,8 +333,6 @@ wire select_call_immediate;                     // Whether to select the call im
 // Functions
 /////////////////////////////////////////////////////
 
-`include "lm32_functions.v"
-
 /////////////////////////////////////////////////////
 // Combinational logic
 /////////////////////////////////////////////////////

diff --git a/verilog/lm32/lm32_functions.v b/verilog/lm32/lm32_functions.v
deleted file mode 100644 (file)
index 1332a6e..0000000
--- a/verilog/lm32/lm32_functions.v
+++ /dev/null
@@ -1,70 +0,0 @@
-//   ==================================================================
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-//   ------------------------------------------------------------------
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-//   ALL RIGHTS RESERVED 
-//   ------------------------------------------------------------------
-//
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-//   Permission:
-//
-//      Lattice Semiconductor grants permission to use this code
-//      pursuant to the terms of the Lattice Semiconductor Corporation
-//      Open Source License Agreement.  
-//
-//   Disclaimer:
-//
-//      Lattice Semiconductor provides no warranty regarding the use or
-//      functionality of this code. It is the user's responsibility to
-//      verify the user's design for consistency and functionality through
-//      the use of formal verification methods.
-//
-//   --------------------------------------------------------------------
-//
-//                  Lattice Semiconductor Corporation
-//                  5555 NE Moore Court
-//                  Hillsboro, OR 97214
-//                  U.S.A
-//
-//                  TEL: 1-800-Lattice (USA and Canada)
-//                         503-286-8001 (other locations)
-//
-//                  web: http://www.latticesemi.com/
-//                  email: techsupport@latticesemi.com
-//
-//   --------------------------------------------------------------------
-//                         FILE DETAILS
-// Project      : LatticeMico32
-// File         : lm32_functions.v
-// Title        : Common functions
-// Version      : 6.1.17
-//              : Initial Release
-// Version      : 7.0SP2, 3.0
-//              : No Change
-// Version      : 3.5
-//              : Added function to generate log-of-two that rounds-up to
-//              : power-of-two
-// =============================================================================
-                                         
-function integer clogb2;
-input [31:0] value;
-begin
-   for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
-        value = value >> 1;
-end
-endfunction 
-
-function integer clogb2_v1;
-input [31:0] value;
-reg   [31:0] i;
-reg   [31:0] temp;
-begin
-   temp = 0;
-   i    = 0;
-   for (i = 0; temp < value; i = i + 1)  
-       temp = 1<<i;
-   clogb2_v1 = i-1;
-end
-endfunction
-

diff --git a/verilog/lm32/lm32_icache.v b/verilog/lm32/lm32_icache.v
index 9f1a759893bf6ca565f79bc57c0c6c576f3d1755..412ee9044a748ecfe1a67d9b049e90f2891b0780 100644 (file)
--- a/verilog/lm32/lm32_icache.v
+++ b/verilog/lm32/lm32_icache.v
@@ -119,14 +119,14 @@ parameter bytes_per_line = 16;                          // Number of bytes per c
 parameter base_address = 0;                             // Base address of cachable memory
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
 
-localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
-localparam addr_set_width = clogb2(sets)-1;
+localparam addr_offset_width = $clog2(bytes_per_line)-2;
+localparam addr_set_width = $clog2(sets);
 localparam addr_offset_lsb = 2;
 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
 localparam addr_set_lsb = (addr_offset_msb+1);
 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
 localparam addr_tag_lsb = (addr_set_msb+1);
-localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1;
+localparam addr_tag_msb = $clog2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS);
 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
 
 /////////////////////////////////////////////////////
@@ -205,8 +205,6 @@ genvar i;
 // Functions
 /////////////////////////////////////////////////////
 
-`include "lm32_functions.v"
-
 /////////////////////////////////////////////////////
 // Instantiations
 /////////////////////////////////////////////////////

diff --git a/verilog/lm32/lm32_instruction_unit.v b/verilog/lm32/lm32_instruction_unit.v
index 10a2d9c9638f76bc06e39937df87727801afb4a6..4f688c108bbf7d9ca1121569f31dbc9ad013aae8 100644 (file)
--- a/verilog/lm32/lm32_instruction_unit.v
+++ b/verilog/lm32/lm32_instruction_unit.v
@@ -179,7 +179,7 @@ parameter base_address = 0;                             // Base address of cacha
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
 
 // For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
-localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : $clog2(bytes_per_line)-2;
 localparam addr_offset_lsb = 2;
 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
 
@@ -377,8 +377,6 @@ reg alternate_eba_taken;
 // Functions
 /////////////////////////////////////////////////////
 
-`include "lm32_functions.v"
-
 /////////////////////////////////////////////////////
 // Instantiations
 /////////////////////////////////////////////////////
@@ -390,18 +388,18 @@ reg alternate_eba_taken;
        // ----- Parameters -------
        .pmi_family             (`LATTICE_FAMILY),
         
-       //.pmi_addr_depth_a       (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
-       //.pmi_addr_width_a       ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
+       //.pmi_addr_depth_a       (1 << $clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
+       //.pmi_addr_width_a       ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
        //.pmi_data_width_a       (`LM32_WORD_WIDTH),
-       //.pmi_addr_depth_b       (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
-       //.pmi_addr_width_b       ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
+       //.pmi_addr_depth_b       (1 << $clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
+       //.pmi_addr_width_b       ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
        //.pmi_data_width_b       (`LM32_WORD_WIDTH),
         
        .pmi_addr_depth_a       (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
-       .pmi_addr_width_a       (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
+       .pmi_addr_width_a       ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
        .pmi_data_width_a       (`LM32_WORD_WIDTH),
        .pmi_addr_depth_b       (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
-       .pmi_addr_width_b       (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
+       .pmi_addr_width_b       ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
        .pmi_data_width_b       (`LM32_WORD_WIDTH),
         
        .pmi_regmode_a          ("noreg"),
@@ -420,8 +418,8 @@ reg alternate_eba_taken;
            .ResetB                 (rst_i),
            .DataInA                ({32{1'b0}}),
            .DataInB                (irom_store_data_m),
-           .AddressA               (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
-           .AddressB               (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
+           .AddressA               (pc_a[$clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
+           .AddressB               (irom_address_xm[$clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
            .ClockEnA               (!stall_a),
            .ClockEnB               (!stall_x || !stall_m),
            .WrA                    (`FALSE),

diff --git a/verilog/lm32/lm32_load_store_unit.v b/verilog/lm32/lm32_load_store_unit.v
index 4a86e7b0ab688a6238c1e91d1ab8580f32b75683..088a69b5ff3c63ff5e521d15c7efbfaf89c71371 100644 (file)
--- a/verilog/lm32/lm32_load_store_unit.v
+++ b/verilog/lm32/lm32_load_store_unit.v
@@ -139,7 +139,7 @@ parameter base_address = 0;                             // Base address of cacha
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
 
 // For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
-localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : $clog2(bytes_per_line)-2;
 localparam addr_offset_lsb = 2;
 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
 
@@ -282,8 +282,6 @@ reg wb_load_complete;                                   // Indicates when a Wish
 // Functions
 /////////////////////////////////////////////////////
 
-`include "lm32_functions.v"
-
 /////////////////////////////////////////////////////
 // Instantiations
 /////////////////////////////////////////////////////
@@ -295,18 +293,18 @@ reg wb_load_complete;                                   // Indicates when a Wish
        // ----- Parameters -------
        .pmi_family             (`LATTICE_FAMILY),
 
-       //.pmi_addr_depth_a       (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
-       //.pmi_addr_width_a       ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
+       //.pmi_addr_depth_a       (1 << $clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
+       //.pmi_addr_width_a       ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
        //.pmi_data_width_a       (`LM32_WORD_WIDTH),
-       //.pmi_addr_depth_b       (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
-       //.pmi_addr_width_b       ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
+       //.pmi_addr_depth_b       (1 << $clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
+       //.pmi_addr_width_b       ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
        //.pmi_data_width_b       (`LM32_WORD_WIDTH),
        
        .pmi_addr_depth_a       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
-       .pmi_addr_width_a       (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
+       .pmi_addr_width_a       ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
        .pmi_data_width_a       (`LM32_WORD_WIDTH),
        .pmi_addr_depth_b       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
-       .pmi_addr_width_b       (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
+       .pmi_addr_width_b       ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
        .pmi_data_width_b       (`LM32_WORD_WIDTH),
 
        .pmi_regmode_a          ("noreg"),
@@ -325,8 +323,8 @@ reg wb_load_complete;                                   // Indicates when a Wish
            .ResetB                 (rst_i),
            .DataInA                ({32{1'b0}}),
            .DataInB                (dram_store_data_m),
-           .AddressA               (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
-           .AddressB               (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
+           .AddressA               (load_store_address_x[$clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
+           .AddressB               (load_store_address_m[$clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
            // .ClockEnA               (!stall_x & (load_x | store_x)),
            .ClockEnA               (!stall_x),
            .ClockEnB               (!stall_m),

diff --git a/verilog/lm32/lm32_top.v b/verilog/lm32/lm32_top.v
index c03e280bff6dda462c0aba2baefe322204b5eb46..bc2bdf52cdbfb363c584ce92a506a5d978976554 100644 (file)
--- a/verilog/lm32/lm32_top.v
+++ b/verilog/lm32/lm32_top.v
@@ -242,7 +242,6 @@ wire trace_bret;                                // Indicates a bret instruction
 // Functions
 /////////////////////////////////////////////////////
 
-`include "lm32_functions.v"
 /////////////////////////////////////////////////////
 // Instantiations
 /////////////////////////////////////////////////////