add more instructions for vector exception handling

diff --git a/riscv/insns/vwaitxcpt.h b/riscv/insns/vwaitxcpt.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/vxcptevac.h b/riscv/insns/vxcptevac.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vxcpthold.h b/riscv/insns/vxcpthold.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vxcptkill.h b/riscv/insns/vxcptkill.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vxcptwait.h b/riscv/insns/vxcptwait.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/opcodes.h b/riscv/opcodes.h
index 16004778449b7381654ef7a4fcdc0804410396e4..1e4881f25fc3db4d39a748845dca448b5711ef79 100644 (file)
--- a/riscv/opcodes.h
+++ b/riscv/opcodes.h
@@ -37,7 +37,7 @@ DECLARE_INSN(c_li, 0x0, 0x1f)
 DECLARE_INSN(di, 0xfb, 0x7ffffff)
 DECLARE_INSN(sltiu, 0x193, 0x3ff)
 DECLARE_INSN(mtpcr, 0x1fb, 0xf801ffff)
-DECLARE_INSN(vlb, 0xb, 0x3fffff)
+DECLARE_INSN(vxcptwait, 0x1817b, 0xffffffff)
 DECLARE_INSN(stop, 0x177, 0xffffffff)
 DECLARE_INSN(vld, 0x18b, 0x3fffff)
 DECLARE_INSN(c_slli, 0x19, 0x1c1f)
@@ -47,6 +47,7 @@ DECLARE_INSN(fcvt_s_w, 0xe053, 0x3ff1ff)
 DECLARE_INSN(vflstw, 0x150b, 0x1ffff)
 DECLARE_INSN(mul, 0x433, 0x1ffff)
 DECLARE_INSN(c_lw, 0xa, 0x1f)
+DECLARE_INSN(vxcptevac, 0x1807b, 0xf83fffff)
 DECLARE_INSN(vlw, 0x10b, 0x3fffff)
 DECLARE_INSN(vssegstw, 0x90f, 0xfff)
 DECLARE_INSN(amominu_d, 0x19ab, 0x1ffff)
@@ -85,6 +86,7 @@ DECLARE_INSN(vsetvl, 0x2f3, 0x3fffff)
 DECLARE_INSN(fle_d, 0x170d3, 0x1ffff)
 DECLARE_INSN(fence_i, 0xaf, 0x3ff)
 DECLARE_INSN(vlsegbu, 0x220b, 0x1ffff)
+DECLARE_INSN(vlsegstb, 0x80b, 0xfff)
 DECLARE_INSN(fnmsub_d, 0xcb, 0x1ff)
 DECLARE_INSN(addw, 0x3b, 0x1ffff)
 DECLARE_INSN(sll, 0xb3, 0x1ffff)
@@ -105,7 +107,6 @@ DECLARE_INSN(addi, 0x13, 0x3ff)
 DECLARE_INSN(vfmst, 0x1173, 0x1ffff)
 DECLARE_INSN(mulh, 0x4b3, 0x1ffff)
 DECLARE_INSN(fmul_s, 0x2053, 0x1f1ff)
-DECLARE_INSN(vwaitxcpt, 0x1807b, 0xffffffff)
 DECLARE_INSN(vlsegsthu, 0xa8b, 0xfff)
 DECLARE_INSN(srai, 0x10293, 0x3f03ff)
 DECLARE_INSN(amoand_d, 0x9ab, 0x1ffff)
@@ -181,6 +182,7 @@ DECLARE_INSN(fcvt_d_lu, 0xd0d3, 0x3ff1ff)
 DECLARE_INSN(amomax_d, 0x15ab, 0x1ffff)
 DECLARE_INSN(fcvt_w_d, 0xa0d3, 0x3ff1ff)
 DECLARE_INSN(fmovz, 0xaf7, 0x1ffff)
+DECLARE_INSN(feq_d, 0x150d3, 0x1ffff)
 DECLARE_INSN(c_or3, 0x21c, 0x31f)
 DECLARE_INSN(vmvv, 0x73, 0x3fffff)
 DECLARE_INSN(vfssegstw, 0xd0f, 0xfff)
@@ -214,7 +216,7 @@ DECLARE_INSN(vfmvv, 0x173, 0x3fffff)
 DECLARE_INSN(vlstwu, 0x130b, 0x1ffff)
 DECLARE_INSN(c_sub3, 0x11c, 0x31f)
 DECLARE_INSN(vsh, 0x8f, 0x3fffff)
-DECLARE_INSN(vlsegstb, 0x80b, 0xfff)
+DECLARE_INSN(vlb, 0xb, 0x3fffff)
 DECLARE_INSN(vlsegstd, 0x98b, 0xfff)
 DECLARE_INSN(vflsegd, 0x258b, 0x1ffff)
 DECLARE_INSN(vflsegw, 0x250b, 0x1ffff)
@@ -229,6 +231,7 @@ DECLARE_INSN(vmst, 0x1073, 0x1ffff)
 DECLARE_INSN(fadd_d, 0xd3, 0x1f1ff)
 DECLARE_INSN(fcvt_s_wu, 0xf053, 0x3ff1ff)
 DECLARE_INSN(rdnpc, 0x26b, 0x7ffffff)
+DECLARE_INSN(vxcpthold, 0x181fb, 0xffffffff)
 DECLARE_INSN(fcvt_s_l, 0xc053, 0x3ff1ff)
 DECLARE_INSN(vflsegstd, 0xd8b, 0xfff)
 DECLARE_INSN(c_add, 0x1a, 0x801f)
@@ -239,7 +242,7 @@ DECLARE_INSN(fmadd_s, 0x43, 0x1ff)
 DECLARE_INSN(fcvt_w_s, 0xa053, 0x3ff1ff)
 DECLARE_INSN(vssegh, 0x208f, 0x1ffff)
 DECLARE_INSN(fsqrt_s, 0x4053, 0x3ff1ff)
-DECLARE_INSN(feq_d, 0x150d3, 0x1ffff)
+DECLARE_INSN(vxcptkill, 0x180fb, 0xffffffff)
 DECLARE_INSN(c_srai, 0x1019, 0x1c1f)
 DECLARE_INSN(amomin_w, 0x112b, 0x1ffff)
 DECLARE_INSN(fsgnjn_s, 0x6053, 0x1ffff)