x86: Add a ld/st microop flag for marking an access uncacheable.

This percolates down to the memory request object which will have its
"UNCACHEABLE" flag set.

Change-Id: Ie73f4249bfcd57f45a473f220d0988856715a9ce
Reviewed-on: https://gem5-review.googlesource.com/9881
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index 83e24e154c37621937342d1ecd2fddf939e4cfe1..60c6d291bfd6cd8570b2bb979b59fb459298e818 100644 (file)
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -295,7 +295,7 @@ let {{
     class LdStOp(X86Microop):
         def __init__(self, data, segment, addr, disp,
                 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
-                implicitStack):
+                implicitStack, uncacheable):
             self.data = data
             [self.scale, self.index, self.base] = addr
             self.disp = disp
@@ -311,6 +311,8 @@ let {{
                 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
             if nonSpec:
                 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
+            if uncacheable:
+                self.instFlags += " | (Request::UNCACHEABLE)"
             # For implicit stack operations, we should use *not* use the
             # alternative addressing mode for loads/stores if the prefix is set
             if not implicitStack:
@@ -335,7 +337,7 @@ let {{
     class BigLdStOp(X86Microop):
         def __init__(self, data, segment, addr, disp,
                 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
-                implicitStack):
+                implicitStack, uncacheable):
             self.data = data
             [self.scale, self.index, self.base] = addr
             self.disp = disp
@@ -351,6 +353,8 @@ let {{
                 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
             if nonSpec:
                 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
+            if uncacheable:
+                self.instFlags += " | (Request::UNCACHEABLE)"
             # For implicit stack operations, we should use *not* use the
             # alternative addressing mode for loads/stores if the prefix is set
             if not implicitStack:
@@ -383,10 +387,10 @@ let {{
     class LdStSplitOp(LdStOp):
         def __init__(self, data, segment, addr, disp,
                 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
-                implicitStack):
+                implicitStack, uncacheable):
             super(LdStSplitOp, self).__init__(0, segment, addr, disp,
                 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
-                implicitStack)
+                implicitStack, uncacheable)
             (self.dataLow, self.dataHi) = data
 
         def getAllocator(self, microFlags):
@@ -466,10 +470,10 @@ let {{
                     dataSize="env.dataSize",
                     addressSize=addressSize,
                     atCPL0=False, prefetch=False, nonSpec=nonSpec,
-                    implicitStack=implicitStack):
+                    implicitStack=implicitStack, uncacheable=False):
                 super(LoadOp, self).__init__(data, segment, addr,
                         disp, dataSize, addressSize, mem_flags,
-                        atCPL0, prefetch, nonSpec, implicitStack)
+                        atCPL0, prefetch, nonSpec, implicitStack, uncacheable)
                 self.className = Name
                 self.mnemonic = name
 
@@ -547,10 +551,10 @@ let {{
                     dataSize="env.dataSize",
                     addressSize="env.addressSize",
                     atCPL0=False, prefetch=False, nonSpec=nonSpec,
-                    implicitStack=False):
+                    implicitStack=False, uncacheable=False):
                 super(LoadOp, self).__init__(data, segment, addr,
                         disp, dataSize, addressSize, mem_flags,
-                        atCPL0, prefetch, nonSpec, implicitStack)
+                        atCPL0, prefetch, nonSpec, implicitStack, uncacheable)
                 self.className = Name
                 self.mnemonic = name
 
@@ -601,10 +605,11 @@ let {{
             def __init__(self, data, segment, addr, disp = 0,
                     dataSize="env.dataSize",
                     addressSize=addressSize,
-                    atCPL0=False, nonSpec=False, implicitStack=implicitStack):
+                    atCPL0=False, nonSpec=False, implicitStack=implicitStack,
+                    uncacheable=False):
                 super(StoreOp, self).__init__(data, segment, addr, disp,
                         dataSize, addressSize, mem_flags, atCPL0, False,
-                        nonSpec, implicitStack)
+                        nonSpec, implicitStack, uncacheable)
                 self.className = Name
                 self.mnemonic = name
 
@@ -665,10 +670,11 @@ let {{
             def __init__(self, data, segment, addr, disp = 0,
                     dataSize="env.dataSize",
                     addressSize="env.addressSize",
-                    atCPL0=False, nonSpec=False, implicitStack=False):
+                    atCPL0=False, nonSpec=False, implicitStack=False,
+                    uncacheable=False):
                 super(StoreOp, self).__init__(data, segment, addr, disp,
                         dataSize, addressSize, mem_flags, atCPL0, False,
-                        nonSpec, implicitStack)
+                        nonSpec, implicitStack, uncacheable)
                 self.className = Name
                 self.mnemonic = name
 
@@ -696,7 +702,8 @@ let {{
         def __init__(self, data, segment, addr, disp = 0,
                 dataSize="env.dataSize", addressSize="env.addressSize"):
             super(LeaOp, self).__init__(data, segment, addr, disp,
-                    dataSize, addressSize, "0", False, False, False, False)
+                    dataSize, addressSize, "0",
+                    False, False, False, False, False)
             self.className = "Lea"
             self.mnemonic = "lea"
 
@@ -717,7 +724,7 @@ let {{
                 addressSize="env.addressSize"):
             super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
                     addr, disp, dataSize, addressSize, "0", False, False,
-                    False, False)
+                    False, False, False)
             self.className = "Tia"
             self.mnemonic = "tia"
 
@@ -729,7 +736,7 @@ let {{
                 addressSize="env.addressSize", atCPL0=False):
             super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
                     addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
-                    atCPL0, False, False, False)
+                    atCPL0, False, False, False, False)
             self.className = "Cda"
             self.mnemonic = "cda"