pipistrello: compress and load bitstream at 6MHz

diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py
index 65e8d1067b626934f6038cd6cf6966d6435b8c83..9c2aed2434efc2a09a8bd1e5d704ab216fafc38f 100644 (file)
--- a/mibuild/platforms/pipistrello.py
+++ b/mibuild/platforms/pipistrello.py
@@ -130,6 +130,7 @@ class Platform(XilinxPlatform):
 
        def __init__(self):
                XilinxPlatform.__init__(self, "xc6slx45-csg324-2", _io, _connectors)
+               self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"
 
        def create_programmer(self):
                return XC3SProg("papilio", "bscan_spi_lx45_csg324.bit")