Added GP_DELAY cell
authorAndrew Zonenberg <azonenberg@drawersteak.com>
Sun, 8 May 2016 04:29:26 +0000 (21:29 -0700)
committerAndrew Zonenberg <azonenberg@drawersteak.com>
Sun, 8 May 2016 04:29:26 +0000 (21:29 -0700)
techlibs/greenpak4/cells_sim.v

index b9cfbe66564bd065350f1640ff03b7941dbbfc08..be8e66c66b551380d26fac73998a5cd45c88d518 100644 (file)
@@ -94,6 +94,35 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 
 endmodule
 
+module GP_DELAY(input IN, output reg OUT);
+       
+       parameter DELAY_STEPS = 1;
+       
+       //TODO: additional delay/glitch filter mode
+       
+       initial OUT = 0;
+       
+       generate
+               
+               //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
+               //Change simulation-mode delay depending on global Vdd range (how to specify this?)
+               always @(*) begin
+                       case(DELAY_STEPS)
+                               1: #166 OUT = IN;
+                               2: #318 OUT = IN;
+                               2: #471 OUT = IN;
+                               3: #622 OUT = IN;
+                               default: begin
+                                       $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
+                                       $finish;
+                               end
+                       endcase
+               end
+               
+       endgenerate
+       
+endmodule
+
 module GP_DFF(input D, CLK, output reg Q);
        parameter [0:0] INIT = 1'bx;
        initial Q = INIT;